Abstract: Systems and methods for electroless deposition of a cobalt-alloy layer on a copper surface include a solution characterized by a low pH. This solution may include, for example, a cobalt(II) salt, a complexing agent including at least two amine groups, a pH adjuster configured to adjust the pH to below 7.0, and a reducing agent. In some embodiments, the cobalt-alloy is configured to facilitate bonding and copper diffusion characteristics between the copper surface and a dielectric in an integrated circuit.

Abstract: A method for etching features in a silicon oxide based dielectric layer over a substrate, comprising performing an etch cycle. A lag etch partially etching features in the silicon oxide based dielectric layer is performed, comprising providing a lag etchant gas, forming a plasma from the lag etchant gas, and etching the etch layer with the lag etchant gas, so that smaller features are etched slower than wider features. A reverse lag etch further etching the features in the silicon oxide based dielectric layer is performed comprising providing a reverse lag etchant gas, which is different from the lag etchant gas and is more polymerizing than the lag etchant gas, forming a plasma from the reverse lag etchant gas, and etching the silicon oxide based dielectric layer with the plasma formed from the reverse lag etchant gas, so that smaller features are etched faster than wider features.

Abstract: Compositions and methods for forming metal films on semiconductor substrates are disclosed. One of the disclosed methods comprises: heating the semiconductor substrate to obtain a heated semiconductor substrate; exposing the heated semiconductor substrate to a composition containing at least one metal precursor comprising at least one ligand, an excess amount of neutral labile ligands, a supercritical solvent, and optionally at least one source of B, C, N, Si, P, and mixtures thereof; exposing the composition to a reducing agent and/or thermal energy at or near the heated semiconductor substrate; disassociating the at least one ligand from the metal precursor; and forming the metal film while minimizing formation of metal oxides.

Abstract: A gas delivery apparatus having a manifold block configured to create a fluid flow path, a horizontal inlet port coupled to the manifold block at a first side in fluid communication with the fluid flow path and configured to receive a supply gas, a pneumatic valve coupled to the manifold block at a first end configured to prevent unauthorized activation of fluid flow, the pneumatic valve in fluid communication with the fluid flow path and horizontal inlet port, a purge valve coupled to the manifold block in fluid communication with the fluid flow path positioned adjacent the pneumatic valve, and a vertical purge port coupled to the manifold block at a first end, the vertical purge port positioned between the purge valve and the pneumatic valve and having a purge gas input/output connection at a second end, wherein the horizontal inlet port is positioned perpendicular to the vertical purge port.

Abstract: A method for etching a dielectric layer disposed below an antireflection layer (ARL) is provided. The method comprises (a) forming a patterned mask with mask features over the ARL, the mask having isolated areas and dense areas of the mask features, (b) trimming and opening, and (c) etching the dielectric layer using the trimmed mask. The trimming and opening comprises a plurality of cycles, where each cycle includes (b1) a trim-etch phase which etches the ARL in a bottom of the mask features and selectively trims the isolated areas of the mask with respect to the dense areas, and (b2) a deposition-etch phase which deposits a deposition layer on the mask while further etching the ARL in the bottom of the mask features. The trimming and opening result in a net trimming of the mask in the isolated areas.

Abstract: Disclosed is a method for processing a two layer mask for use in fabrication of semiconductor devices whereby the critical dimension (CD) of a semiconductor device being fabricated with the mask can be controlled. After forming a carbon mask layer and a silicon containing photoresist layer on the carbon mask, a two-step process forms openings in the carbon mask layer, as required for subsequent device fabrication. The structure is placed in a plasma processing chamber, and an oxygen plasma is employed to partially etch the carbon layer. The oxygen plasma reacts with silicon in the photoresist to form a hard silicon oxide layer on the surface of the photoresist. A hydrogen plasma is then employed to complete the etch through the carbon layer with a reduced critical dimension. Damage to the silicon containing photoresist layer is kept to a minimum during the plasma etch process by limiting the low frequency RF power.

Abstract: A plasma processing system for plasma processing of substrates such as semiconductor wafers. The system includes a plasma processing chamber, a substrate support for supporting a substrate within the processing chamber, a dielectric member having an interior surface facing the substrate support, the dielectric member forming a wall of the processing chamber, a gas injector fixed to, part of or removably mounted in an opening in the dielectric window, the gas injector including a plurality of gas outlets supplying process gas into the chamber, and an RF energy source such as a planar or non-planar spiral coil which inductively couples RF energy through the dielectric member and into the chamber to energize the process gas into a plasma state. The arrangement permits modification of gas delivery arrangements to meet the needs of a particular processing regime. In addition, compared to consumable showerhead arrangements, the use of a removably mounted gas injector can be replaced more easily and economically.

Abstract: Particles are trapped away from a wafer transport zone in a chamber. A first electrode is on one side of the zone. A second electrode is on an opposite side of the zone. A power supply connected across the electrodes establishes an electrostatic field between the electrodes. The field traps particles at the electrodes, away from the zone. For transporting the wafer from the chamber, the second electrode mounts the wafer for processing, and the first electrode is opposite to the second electrode defining a process space. The zone is in the space with a separate part of the space separating the zone from each electrode. Particles are urged away from the wafer by simultaneously terminating plasma processing of the wafer, connecting the second electrode to ground, applying a positive DC potential to the first electrode, and de-chucking the wafer from the second electrode into the zone.

Abstract: An electroless deposition chemical system includes an electroless solution including a metal component, and a strongly adsorbed species component having a concentration less than a concentration of the metal component.

Abstract: A plasma processing system for processing a substrate is described. The plasma processing system includes a bottom piece including a chuck configured for holding the substrate. The plasma processing system also includes an induction coil configured to generate an electromagnetic field in order to create a plasma for processing the substrate; and an optimized top piece coupled to the bottom piece, the top piece further configured for a heating and cooling system. Wherein, the heating and cooling system is substantially shielded from the electromagnetic field by the optimized top piece, and the optimized top piece can substantially be handled by a single person.

Abstract: A substrate holding and transporting assembly is disclosed. The substrate holding and transporting assembly includes a base plate and a pair of clamps connected to the base plate in a spaced apart orientation, the spaced apart orientation of the pair of clamps enable support of a substrate with at least two independent points. The substrate holding and transporting assembly also includes an electrode assembly connected to the base plate at a location that is substantially between the pair of clamps. The electrode assembly defined to impart an electrical contact to the substrate when present and held by the pair of clamps.

Abstract: A method is provided which includes dispensing a deposition solution at a plurality of locations extending different distances from a center of a microelectronic topography each at different moments in time during an electroless plating process. An electroless plating apparatus used for the method includes a substrate holder, a moveable dispense arm, and a storage medium comprising program instructions executable by a processor for positioning the moveable dispense arm. Another method and accompanying electroless deposition chamber are configured to introduce a gas into an electroless plating chamber above a plate which is suspended above a microelectronic topography and distribute the gas to regions extending above one or more discrete portions of the microelectronic topography.

Abstract: A wafer viewer system is provided for graphical presentation and analysis of a wafer and a wafer series. More specifically, the wafer viewer system includes a graphical user interface for displaying a wafer, graphically selecting regions of the wafer for analysis, performing analysis on the selected regions of the wafer, and displaying results of the analysis.

Abstract: Characterizing dielectric properties of a part includes placing a full-sized part within a dielectric property measurement apparatus. In one embodiment, the full-sized part is a dielectric part of a plasma processing system. The dielectric property measurement apparatus is operated to determine a dielectric constant value of the full-sized part and a loss tangent value of the full-sized part. The determined dielectric constant and loss tangent values are affixed to the full-sized part.

Abstract: Disclosed is an apparatus for wet treatment of a disc-like article, which comprises: a spin chuck for holding and rotating the disc-like article, and an inner edge nozzle dispensing treatment liquid directed towards a first peripheral region of the first surface of the disc-like article, wherein the first surface is facing the spin chuck and the first peripheral region is defined as being a region of the first surface with an inner radius (ri), which is greater than 1 cm less than the disc-like article's radius (ra), wherein the inner edge nozzle is positioned in a stationary manner between the disc-like article (when placed on the spin chuck) and the spin chuck, wherein the inner edge nozzle is feed through a central pipe, which is disposed in a stationary manner and penetrates centrally through the spin chuck, for supplying a treatment liquid against a first surface of the disc-like article.

Abstract: A semiconductor system includes: providing a dielectric layer; providing a conductor in the dielectric layer, the conductor exposed at the top of the dielectric layer; capping the exposed conductor; and modifying the surface of the dielectric layer, modifying the surface of the dielectric layer, wherein modifying the surface includes cleaning conductor ions from the dielectric layer by dissolving the conductor in a low pH solution, dissolving the dielectric layer under the conductor ions, mechanically enhanced cleaning, or chemisorbing a hydrophobic layer on the dielectric layer.

Abstract: An etch layer underlying a patterned photoresist mask is provided. A plurality of sidewall forming processes are performed. Each sidewall forming process comprises depositing a protective layer on the patterned photoresist mask by performing multiple cyclical depositions. Each cyclical deposition involves at least a depositing phase for depositing a deposition layer over surfaces of the patterned photoresist mask and a profile shaping phase for shaping vertical surfaces in the deposition layer. Each sidewall forming process further comprises a breakthrough etch for selectively etching horizontal surfaces of the protective layer with respect to vertical surfaces of the protective layer. Afterwards, the etch layer is etched to form a feature having a critical dimension that is less than the critical dimension of the features in the patterned photoresist mask.

Abstract: A plasma processing system is disclosed. The plasma processing system may include an electrostatic chuck (ESC) positioned inside a plasma processing chamber and configured to support a wafer. The ESC may include a positive terminal (+ESC) for providing a first force to the wafer and a negative terminal (?ESC) for providing a second force to the wafer. The plasma processing system may also include a first trans-impedance amplifier (TIA) and a second TIA configured to measure a first set of voltages for calculating a value of a positive load current applied to the positive terminal. The plasma processing system may also include a third TIA and a fourth TIA configured to measure a second set of voltages for calculating a value of a negative load current applied to the negative terminal.

Abstract: Apparatus to clean silicon electrode assembly surfaces which controls or eliminates possible chemical attack of electrode assembly bonding materials, and eliminates direct handling contact with the parts to be cleaned during acid treatment, spray rinse, blow dry, bake and bagging. Aspects of the apparatus include a kit including an electrode carrier to hold an electrode assembly, a treatment stand to allow access to the electrode assembly, a spider plate to clamp the electrode assembly in the electrode carrier, a nitrogen purge plate to supply nitrogen gas to the backside of the electrode assembly during acid cleaning of the electrode, a water rinse plate to supply water to the electrode face, a blow dry plate to supply nitrogen to dry the electrode assembly and a bake stand to support the electrode assembly during a bake before placing the clean electrode assembly in a bag.

Abstract: A method for providing substantially similar chamber condition before each wafer process operation in a semiconductor process chamber is provided. The method allows for prevention of transport of particle and metal contamination from chamber surfaces to the processed wafer. The method initiates with depositing a silicon containing layer over an inner surface of an empty semiconductor process chamber. Then, a wafer is introduced into the semiconductor process chamber after depositing the silicon containing layer. Next, a process operation is performed on the wafer. The process operation deposits a residue on the silicon containing layer. Next, an in-situ cleaning process is initiated upon completion of the processing operation and removal of the wafer.