Abstract: A microelectronic topography includes a dielectric layer (DL) with a surface higher than an adjacent bulk metal feature (BMF) and further includes a barrier layer (BL) upon the BMF and extending higher than the DL. Another microelectronic topography includes a BL with a metal-oxide layer having a metal element concentration which is disproportionate relative to concentrations of the element within metal alloy layers on either side of the metal-oxide layer. A method includes forming a BL upon a BMF such that portions of a first DL adjacent to the BMF are exposed, selectively depositing a second DL upon the BL, cleaning the topography thereafter, and blanket depositing a third DL upon the cleaned topography. Another method includes polishing a microelectronic topography such that a metallization layer is coplanar with a DL and further includes spraying a deionized water based fluid upon the polished topography to remove debris from the DL.

Abstract: Techniques and apparatus for substantially reducing and/or preventing the occurrence of plasma un-confinement events, including one or more of shielding a gap disposed between chamber components and along a RF current path with a dielectric shielding structure, shielding a sharp component structure with a dielectric shielding structure, and keeping the gap between adjacent pairs of plasma confinement rings smaller than the worst-case DeBye length for the plasma.

Abstract: A wafer handling mechanism is operated to place a wafer on a chuck. A chucking force is then applied to the wafer, whereby wafer support features of the chuck transfer a defect pattern onto a surface of the wafer. The surface of the wafer is analyzed by a defect metrology tool to obtain a mapping of the defect pattern transferred onto the surface of the wafer. A center coordinate of the chuck within a coordinate system of the wafer is determined by analyzing the defect pattern as transferred to the surface of the wafer. A spatial offset between the center coordinate of the chuck and the center of the wafer is determined. The spatial offset is used to adjust the wafer handling mechanism so as to enable alignment of the center of the wafer to the center coordinate of the chuck.

Abstract: A method of preventing arcing during bevel edge etching a semiconductor substrate with a plasma in a bevel etcher in which the semiconductor substrate is supported on a semiconductor substrate support comprises bevel edge etching the semiconductor substrate with the plasma in the bevel etcher while evacuating the bevel etcher to a pressure of 3 to 100 Torr while maintaining RF voltage seen at the wafer at a low enough value to avoid arcing.

Abstract: A plasma processing apparatus includes a heater in thermal contact with a showerhead electrode, and a temperature controlled top plate in thermal contact with the heater to maintain a desired temperature of the showerhead electrode during semiconductor substrate processing. A gas distribution member supplies a process gas and radio frequency (RF) power to the showerhead electrode.

Abstract: A method for forming a feature in an etch layer is provided. A photoresist layer is formed over the etch layer. The photoresist layer is patterned to form photoresist features with photoresist sidewalls. A control layer is formed over the photoresist layer and bottoms of the photoresist features. A conformal layer is deposited over the sidewalls of the photoresist features and control layer to reduce the critical dimensions of the photoresist features. Openings in the control layer are opened with a control layer breakthrough chemistry. Features are etched into the etch layer with an etch chemistry, which is different from the control layer break through chemistry, wherein the control layer is more etch resistant to the etch with the etch chemistry than the conformal layer.

Abstract: A method is provided for removing contamination from a substrate. The method includes applying a cleaning solution having a dispersed phase, a continuous phase and particles dispersed within the continuous phase to a surface of the substrate. The method includes forcing one of the particles dispersed within the continuous phase proximate to one of the surface contaminants. The forcing is sufficient to overcome any repulsive forces between the particles and the surface contaminants so that the one of the particles and the one of the surface contaminants are engaged. The method also includes removing the engaged particle and surface contaminant from the surface of the substrate. A process to manufacture the cleaning material is also provided.

Abstract: According to one embodiment of the present invention, a method of cleaning one or more fluid plenums of an electrode assembly is provided. According to the method, a plurality of fluid ports in communication with the fluid plenum are isolated and differentiated into respective sets of plenum input ports and plenum output ports. The input and output ports are engaged with respective cleaning fluid couplings. A cleaning fluid is directed through the fluid plenum by creating a fluid pressure differential ?P=PIN?POUT across the plenum input and output ports. The pressure differential ?P is large enough to force cleaning fluid from the cleaning fluid supply duct to the cleaning fluid waste duct through the fluid plenum. Additional embodiments are disclosed and claimed.

Abstract: A brush core for use in cleaning a substrate is provided. The brush core includes an elongated cylinder having a first end and a second end. The first end of the elongated cylinder is configured to receive a drive hub. The second end is configured to receive fluid into an inner cavity of the elongated cylinder. The inner cavity is configured to distribute fluid to a plurality of fluid channels having a first diameter. The plurality of fluid channels are configured to distribute the fluid to corresponding distribution holes having a second diameter. The brush core further including a plurality of non-fluid distributing pockets defined on the outer surface. The corresponding distribution holes and plurality of non-fluid distributing pockets are configured so that a thickness of a solid portion of the brush core is substantially similar. In one embodiment, the first diameter is less than the second diameter.

Abstract: A wafer viewer system is provided for graphical presentation and analysis of a wafer and a wafer series. More specifically, the wafer viewer system includes a graphical user interface for displaying a wafer, graphically selecting regions of the wafer for analysis, performing analysis on the selected regions of the wafer, and displaying results of the analysis.

Abstract: A process for cleaning a silicon electrode is provided where the silicon electrode is soaked in an agitated aqueous detergent solution and rinsed with water following removal from the aqueous detergent solution. The rinsed silicon electrode is then soaked in an agitated isopropyl alcohol (IPA) solution and rinsed. The silicon electrode is then subjected to an ultrasonic cleaning operation in water following removal from the IPA solution. Contaminants are then removed from the silicon electrode by soaking the silicon electrode in an agitated mixed acid solution comprising hydrofluoric acid, nitric acid, acetic acid, and water. The silicon electrode is subjected to an additional ultrasonic cleaning operation following removal from the mixed acid solution and is subsequently rinsed and dried. In other embodiments of the present disclosure, it is contemplated that the silicon electrode can be soaked in either the agitated aqueous detergent solution, the agitated isopropyl alcohol (IPA) solution, or both.

Abstract: A process is provided for polishing a silicon electrode utilizing a polishing turntable and a dual function electrode platen. The dual function electrode platen is secured to the polishing turntable and comprises a plurality of electrode mounts arranged to project from an electrode engaging face of the dual function electrode platen. The electrode mounts complement respective positions of mount receptacles formed in a platen engaging face of the silicon electrode to be polished. The electrode mounts and the mount receptacles are configured to permit non-destructive engagement and disengagement of the electrode engaging face of the electrode platen and the platen engaging face of the silicon electrode. The dual function electrode platen further comprises platen adapter abutments positioned radially inward of the electrode mounts. The platen adapter abutments are configured to bring a platen adapter into approximate alignment with the rotary polishing axis.

Abstract: A plasma processing chamber includes a cantilever assembly configured to neutralize atmospheric load. The chamber includes a wall surrounding an interior region and having an opening formed therein. A cantilever assembly includes a substrate support for supporting a substrate within the chamber. The cantilever assembly extends through the opening such that a portion is located outside the chamber. The chamber includes an actuation mechanism operative to move the cantilever assembly relative to the wall.

Abstract: Methods for processing a substrate with a fluid meniscus are provided. One method includes positioning a transition surface substantially coplanar to a substrate surface. The transition surface is defined to be adjacent to an edge of the substrate. And, moving a fluid meniscus between the transition surface and the substrate surface.

Abstract: Methods for cleaning semiconductor wafers following chemical mechanical polishing are provided. An exemplary method exposes a wafer to a thermal treatment in an oxidizing environment followed by a thermal treatment in a reducing environment. The thermal treatment in the oxidizing environment both removes residues and oxidizes exposed copper surfaces to form a cupric oxide layer. The thermal treatment in the reducing environment then reduces the cupric oxide to elemental copper. This leaves the exposed copper clean and in condition for further processing, such as electroless plating.

Abstract: A method for etching an ultra high aspect ratio feature in a dielectric layer through a carbon based mask is provided. The dielectric layer is selectively etched with respect to the carbon based mask, wherein the selective etching provides a net deposition of a fluorocarbon based polymer on the carbon based mask. The selective etch is stopped. The fluorocarbon polymer is selectively removed with respect to the carbon based mask, so that the carbon based mask remains, using a trimming. The selectively removing the fluorocarbon polymer is stopped. The dielectric layer is again selectively etched with respect to the carbon based mask, wherein the second selectively etching provides a net deposition of a fluorocarbon based polymer on the carbon based mask.

Abstract: A device for liquid treatment of a defined area of a wafer-shaped article, especially of a wafer, near the edge, in which the liquid is applied to a first surface, flows essentially radially to the outside to the peripheral-side edge of the wafer-shaped article and around this edge onto the second surface, the liquid wetting a defined section near the edge on the second surface and thereupon being removed from the wafer-shaped article.

Abstract: A number of RF power transmission paths are defined to extend from an RF power source through a matching network, through a transmit electrode, through a plasma to a number of return electrodes. A number of tuning elements are respectively disposed within the number of RF power transmission paths. Each tuning element is defined to adjust an amount of RF power to be transmitted through the RF power transmission path within which the tuning element is disposed. A plasma density within a vicinity of a particular RF power transmission path is directly proportional to the amount of RF power transmitted through the particular RF power transmission path. Therefore, adjustment of RF power transmitted through the RF power transmission paths, as afforded by the tuning element, enables control of a plasma density profile across a substrate.

Abstract: Universal plasma unconfinement detection systems configured to detect the plasma unconfinement condition in the plasma processing chamber and methods therefor. The detection systems and methods are designed to reliably and accurately detect the existence of the plasma unconfinement condition in a process-independent and recipe-independent manner.

Abstract: A plasma processing chamber with a probe apparatus configured to measure a set of electrical characteristics in a plasma is disclosed. The plasma processing chamber includes a set of plasma chamber surfaces configured to be exposed to the plasma. The probe apparatus includes a collection disk structure configured to be exposed to the plasma, whereby the collection disk structure is coplanar with at least one of the set of plasma chamber surfaces. The probe apparatus also includes a conductive path configured to transmit the set of electrical characteristics from the collection disk structure to a set of transducers.