Abstract: A video processing device is configured to: generate a frame number which represents a frame to which video data belong and a value of which changes between consecutive frames; for each data block of a predetermined size in the video data, embed the frame number in a portion of the data block; write, in a frame order, the video data into a memory by using a data block as a unit; successively read data blocks written into the memory; and generate an abnormality determination signal indicating frozen video in a case where a state in which the frame number in the data block currently read does not change from the frame number in the data block read last time continues for a predetermined number of times or more.

Abstract: A circuit includes: a receiving circuit, having a first input terminal for inputting a first signal transmitted via a first capacitive element, and a second input terminal for inputting a second signal transmitted via a second capacitive element and having a potential that changes complementarily to the first signal, and outputting a first logic signal corresponding to a potential of the first signal and a second logic signal corresponding to a potential of the second signal; and a signal supply circuit, supplying a first guarantee signal having a potential corresponding to a value of the first logic signal to the first input terminal as a signal for guaranteeing a potential of the first signal, and supplying a second guarantee signal having a potential that changes complementarily to the first guarantee signal to the second input terminal as a signal for guaranteeing a potential of the second signal.

Abstract: The disclosure includes: a differential amplifier, and a first decoder assigning and supplying a first or second voltage to each of a plurality of input terminals based on (K+1) bits of digital data. The differential amplifier includes 2K differential pairs each driven by a tail current received individually, and a tail current control circuit supplying first to 2Kth tail currents to the 2K differential pairs and controlling first to 2Kth current ratios for the first to 2Kth tail currents based on the digital data. The tail current control circuit has a basic configuration that sets each of the first to 2Kth current ratios to a maximum value, a minimum value, or an intermediate value among three predetermined values, and increases one of the maximum and minimum values and decreases the other for the current ratio of the tail currents supplied to two predetermined differential pairs.

Abstract: A video signal transmission device including: an imaging device that is an imaging device including pixels of plural colors arrayed in the same line, and that outputs RAW data generated by performing imaging; a conversion section that takes the RAW data output from the imaging device and rearranges pixel data such that pixel data of the same color is contiguous for each set of plural lines of a first direction; a digital-to-analog conversion section that converts digital data that has been converted by the conversion section into an analogue signal; and a transmission section that transmits the analogue signal that has been converted by the digital-to-analog conversion section.

Abstract: A transmission system including a transmission device capable of transmitting a video signal, and a reception device capable of receiving the video signal transmitted by the transmission device, the transmission system includes: a processor connected to a memory; a video transmission circuit and a video reception circuit that transmit the video signal between the transmission device and the reception device; a transmission-side data transceiving circuit and a reception-side data transceiving circuit that transmit a data signal between the transmission device and the reception device, wherein the processor is configured to selectively execute a video signal transmission mode in which transmission of the video signal is performed and transmission of the data signal superimposed on the video signal is performed, and a data signal transmission exclusive mode in which transmission of the video signal is stopped and transmission of the data signal is performed.

Abstract: A discharge control circuit includes: a first gate voltage output circuit that outputs a first gate voltage supplied to a transistor connected to a capacitive load; a second gate voltage output circuit that outputs a second gate voltage supplied to the transistor; and a switching control circuit that switches supply of the first gate voltage and the second gate voltage to the transistor. The first gate voltage output circuit includes: a voltage supply circuit that supplies a voltage to a gate of the transistor until the transistor changes from an off state to an on state; and a current supply circuit that supplies a current to the gate of the transistor. The second gate voltage output circuit outputs a voltage at a constant level as the second gate voltage. The switching control circuit performs control to supply the second gate voltage after supplying the first gate voltage to the transistor.

Abstract: A semiconductor device is formed by first and second dies manufactured by processes with different wiring widths and includes: a first switch, outputting an input power voltage when set to ON, and stopping output when set to OFF; and a second switch, outputting, from a second voltage output terminal, the power voltage output to a second voltage input terminal when set to ON and stopping output when set OFF; and at least one retention flip-flop, provided with: a first power terminal, connected with the second voltage output terminal; and a second power terminal, connected with the first voltage output terminal, and maintaining data when the power voltage is supplied to the second power terminal and supply of the power voltage to the first power terminal is cut off. The first switch is formed in a first die, and the second switch and retention flip-flop are formed in a second die.

Abstract: A data communication system includes a transmission circuit including an encoder that receives an information data piece composed of N (N is an integer of 2 or greater) bits and generates a converted information data piece in a serial form composed of first to N-th bits representing a value, which is obtained by adding 1 to a value represented by the information data piece, and transmitting an information data signal including the converted information data piece, and a reception circuit including a PLL circuit that receives the information data signal and generates a clock signal that is phase-synchronized with a rising edge or a falling edge of the information data signal, and a decoder that receives the information data signal and subtracts 1 from the value represented by the information data piece included in the information data signal to restore the information data piece.

Abstract: A receiving device includes: first and second antennas; an antenna switching part switching a receiving antenna to the first or second antenna; a frequency conversion part obtaining a baseband signal; a frequency detection part obtaining a frequency detection signal; a data reproduction part generating demodulated data; a synchronization detection part performing synchronization detection based on the demodulated data; a signal strength acquisition part acquiring the signal strength of the received signal; and a switching controller controlling switching based on the signal strength.

Abstract: The disclosure includes a memory, a horizontal synchronization detection circuit, a phase comparator, a lock circuit, a PLL, and a frequency divider. The memory that reads out a written video signal in response to a read clock signal and outputs it as an output video signal. The horizontal synchronization detection circuit detects a horizontal synchronization signal from the video signal. The phase comparator generates a phase difference signal indicating a phase difference between the horizontal synchronization signal and a frequency-divided clock signal. The lock circuit receives a free-running clock signal and generates a reference clock signal in which a phase signal is shifted by an amount of the phase difference indicated by the phase difference signal. The PLL generates the read clock signal that is locked to the phase of the reference clock signal. The frequency divider generates the frequency-divided clock signal by dividing the read clock signal.

Abstract: A digital-to-analog conversion circuit includes a differential amplifier outputting 2N voltage levels dividing first and second voltages and a decoder distributing and supplying one of first and second voltages to a plurality of input terminals of the differential amplifier on the basis of digital data of N bits, and the differential amplifier includes 2K differential pairs including an inverting input terminal to which an output voltage is commonly input and a non-inverting input terminal to which one of voltages received by the plurality of input terminals is input and having output pairs commonly connected with each other and a tail current control circuit individually controlling current ratios of tail currents supplied to the differential pairs on the basis of a predetermined bit of digital data, in which N is equal to or greater than 3, and K is a positive number less than N.

Abstract: An audio reproduction device includes a reproduction control part executing pitch fading processing of changing a frequency of audio during reproduction in stages or volume fading processing of changing a sound volume in stages, a pitch register storing a pitch setting value, a volume register storing a volume setting value, and a fading register storing a step setting value indicating a form of change in the pitch or volume fading processing. The reproduction control part changes the frequency in stages in a form based on the step setting value in response to change of the pitch setting value while having a pitch setting value after change as a target value, and changes the sound volume in stages in a form based on the step setting value in response to change of the volume setting value while having a volume setting value after change as a target value.

Abstract: In a semiconductor device 100, at least one of a first transistor and a second transistor that supply a second voltage in a step-down circuit stepping down a first voltage to the second voltage and outputting the second voltage from an output portion is configured such that the number of second contacts of a source electrode which is connected to a ground voltage or is supplied with the first voltage is larger than the number of first contacts connecting a diffusion layer and a first metal layer of a drain electrode connected to the output portion, and the number of second vias of the source electrode connected to the ground voltage or supplied with the first voltage is larger than the number of first vias connecting the first metal layer and a second metal layer of the drain electrode connected to the output portion.

Abstract: An output buffer circuit includes: a first transistor supplying a first power supply voltage to a first node upon turning on in response to an input signal; a second transistor supplying a second power supply voltage to a second node upon turning on in response to the input signal; a third transistor connecting between the first and second nodes upon turning on in response to a reverse phase signal of a signal on the first node; a fourth transistor connecting between the first and second nodes upon turning on in response to a reverse phase signal of a signal on the second node; a fifth transistor supplying the first power supply voltage upon turning on in response to the signal on the first node; and a sixth transistor supplying the second power supply voltage upon turning on in response to the signal on the second node.

Abstract: A source driver that includes an interface unit that obtains the image data and the frame control signal from a plurality of serial data signals, and outputs the image data and frame control signal and a clock signal, a switch signal generation unit that generates a switch signal in a predetermined section among the image data based on the frame control signal, a selection unit that outputs the clock signal as a write enable signal and outputs a part of the image data as setting data for image data control and timing control in the predetermined section of the image data according to the switch signal, a timing control unit that generates a source timing signal based on the frame control signal, the second clock signal, and the setting data, and a source drive unit that generates drive signals in synchronization with the source timing signal.

Abstract: The disclosure includes: a bias circuit generating first and second bias voltages; a first conductivity type first transistor supplying a first power source voltage to a first node according to the input signal; a second conductivity type second transistor supplying a second power source voltage to a second node according to the input signal; a second conductivity type third transistor receiving the first bias voltage by gate, with source and drain connected to the second and first nodes; a first conductivity type fourth transistor receiving the second bias voltage by gate, with source and drain connected to the first and second nodes; a first conductivity type fifth transistor supplying the first power source voltage to an output terminal according to voltage at the first node; and a second conductivity type sixth transistor supplying the second power source voltage to the output terminal according to voltage at the second node.

Abstract: A delay time control circuit, wherein the delay time control circuit outputs a delay signal to a signal output circuit for outputting a PWM signal to an output circuit, the delay signal being an instruction to stop output of the PWM signal after elapse of a predetermined delay time from an end of a cycle of the PWM signal being output by the signal output circuit.

Abstract: A wireless communication device of the disclosure includes: an antenna, in response to receiving a radio wave, transmitting a radio frequency signal corresponding to the radio wave; a detector, detecting the radio frequency signal to obtain a detection signal; a circuit part, performing signal processing based on reception data obtained by performing demodulation processing on the detection signal; a regulator, in response to receiving an external power source voltage from an external source, generating and supplying an internal power source voltage for operating the circuit part to the circuit part; and a radio wave detection control part, detecting whether or not the antenna is receiving a radio wave and stopping a generation operation of the internal power source voltage by the regulator in response to the antenna not receiving the radio wave.

Abstract: A display driver includes a plurality of DA conversion circuits, amplifiers, and a switch circuit. Each of the DA conversion circuits outputs a gradation reference voltage in a gradation reference voltage group generated by one of gradation reference voltage generating circuits as a gradation voltage. The amplifiers each output a voltage output a voltage obtained by amplifying each gradation voltage as an output voltage. The switch circuit receives an output voltage group output from the amplifiers and a gradation voltage group generated by the respective DA conversion circuits coupled to a specific gradation reference voltage generating circuit. The switch circuit outputs the output voltage group to the display panel when a normal display mode while outputting the gradation voltage group to the display panel when a monochromatic display mode.

Abstract: The differential amplifier circuit includes: first conductivity type first to Nth differential stages each causing a current corresponding to the first or second voltage received at the non-inverting input terminal to flow to a first node and a current corresponding to the output voltage signal received at the inverting input terminal to a second node; a second conductivity type differential stage receiving one of the first and second voltages at the non-inverting input terminal and receiving the output voltage signal at the inverting input terminal, and being activated when the digital data value is within a predetermined range to cause a current corresponding to the one voltage to flow to a third node and a current corresponding to the output voltage signal to a fourth node; and an output amplification stage generating the output voltage signal based on the currents respectively flowing to the first to fourth nodes.