Abstract: A display driver includes: a conversion part which converts first to n-th display data pieces representing a brightness level of each pixel based on an image signal into first to n-th gradation voltages each having a voltage value corresponding to the brightness level and outputs them, where n is an integer of 2 or more; a polarity inversion signal generation circuit which generates a polarity inversion signal for prompting polarity inversion for each frame display period according to the image signal; a first external terminal which receives an operation mode signal representing a test mode or a normal mode; and a first selector which receives a test polarity inversion signal and the polarity inversion signal, selects and outputs the polarity inversion signal when the operation mode signal represents the normal mode, and selects and outputs the test polarity inversion signal when the operation mode signal represents the test mode.

Abstract: The disclosure provides an output circuit, a display driver including the output circuit and a display device. The disclosure includes a PMOS transistor switch that outputs a positive voltage signal from an output terminal when it is turned on, an NMOS transistor switch that outputs a negative voltage signal from the output terminal when it is turned on, and a voltage control circuit that supplies a voltage obtained by shifting the level of a voltage of a source or a drain when the PMOS transistor switch is turned on to a high potential side to a back gate of the PMOS transistor switch and supplies a voltage obtained by shifting the level of a voltage of a source or a drain when the NMOS transistor switch is turned on to a low potential side to a back gate of the NMOS transistor switch.

Abstract: The video signal combining device includes: multiple memory parts each having multiple line memories and respectively acquiring line data of video signals respectively input from multiple input terminals and sequentially writing and storing the acquired line data into the line memories, a reading control part sequentially reading the line data from any one of the line memories in a first-in-first-out manner, and a data output part outputting video combining data in which the line data read by the reading control part is connected. The reading control part reads the line data from determined one of the line memories based on a storage state of the line data in the line memories.

Abstract: A semiconductor device includes a control circuit that includes a regulator output, an error amplifier circuit controlling a first driving transistor that drives the regulator output, and a switching circuit selectively controlling one or more second driving transistors that drive the regulator circuit through the error amplifier circuit. The semiconductor device further includes a switching determination circuit that includes a current source circuit receiving power from a first power line, a current circuit receiving a current from the current source circuit, a capacitor charged or discharged by the current circuit in response to start-up of the regulator output, and a determinator configured to determine a potential of one electrode of the capacitor and generate a determination signal indicating the determination result.

Abstract: The disclosure includes: a bias circuit generating first and second bias voltages; a first conductivity type first transistor supplying a first power source voltage to a first node according to the input signal; a second conductivity type second transistor supplying a second power source voltage to a second node according to the input signal; a second conductivity type third transistor receiving the first bias voltage by gate, with source and drain connected to the second and first nodes; a first conductivity type fourth transistor receiving the second bias voltage by gate, with source and drain connected to the first and second nodes; a first conductivity type fifth transistor supplying the first power source voltage to an output terminal according to voltage at the first node; and a second conductivity type sixth transistor supplying the second power source voltage to the output terminal according to voltage at the second node.

Abstract: A display device includes drivers and a selector that supplies gradation voltage signals to data lines selectively. The source drivers include a first source driver having a first output buffer outputting a switch signal and a second driver having a second output buffer. The first output buffer has first and second transistors connected via an output terminal outputting the switch signal and turned on and off in a complementary manner. The second output buffer has third and fourth transistors connected via an output terminal outputting the switch signal and turned on and off in a complementary manner. The output terminals of the first and second output buffers are electrically connected. The first source driver has a buffer control circuit that controls a voltage to be applied to each transistor in order to create a high-impedance period where the first and second transistors are turned off at the same time.

Abstract: An image processing device has an emphasis processing unit configured to generate an emphasized image yielded by performing an emphasis process on an image captured of surroundings of a vehicle, a smoothing unit configured to generate a smoothed image yielded by performing a smoothing process on the image, and a combination unit configured to generate, for each region of the image, a display image to be displayed in a display using any of the smoothed image, emphasized image, and the image.

Abstract: A semiconductor device, including: a first chip and a second chip that are joined together, a plurality of power domains being configured in the first chip, wherein: the first chip includes a plurality of individual switches and a first connection terminal, the plurality of individual switches being provided in respective correspondence with the plurality of power domains, and the first connection terminal being connected in common to the plurality of individual switches, and the second chip includes a second connection terminal and a common switch, the second connection terminal being connected to the first connection terminal, the common switch being provided between a power supply and the second connection terminal.

Abstract: A semiconductor device configured by bonding a first and a second chip together, including: a first signal output circuit provided at both the first and the second chip and driven by a first drive power; a second signal output circuit provided at both the first and the second chip and driven by a second drive power; a first phase comparison circuit, provided at the first chip, that compares a phase of a first signal and a second signal; a second phase comparison circuit that is provided at the second chip, and that compares a phase of a third signal and a fourth signal; a third phase comparison circuit, provided at the first chip, that compares a phase of a fifth signal and a sixth signal; and a fourth phase comparison circuit, provided at the second chip, that compares a phase of a seventh signal and an eighth signal.

Abstract: A semiconductor device includes: a storage circuit configured to be connected to a regulator circuit having characteristics to be identified using one or more values and store values identifying characteristics of the regulator circuit; and an electronic fuse controller including an input configured to be connected to an electronic fuse circuit including one or more electronic fuses, an output configured to be connected to the storage circuit, a reading control circuit, and a characteristic control circuit, in which the reading control circuit includes a reading circuit configured to read values from at least part of the electronic fuses through the input in a reading period, and the characteristic control circuit is configured to generate identification data configured to identify the characteristics based on a signal from the reading circuit and supply the identification data to the storage circuit through the output in an identifying period different from the reading period.

Abstract: An output buffer circuit includes: a first transistor supplying a first power supply voltage to a first node upon turning on in response to an input signal; a second transistor supplying a second power supply voltage to a second node upon turning on in response to the input signal; a third transistor connecting between the first and second nodes upon turning on in response to a reverse phase signal of a signal on the first node; a fourth transistor connecting between the first and second nodes upon turning on in response to a reverse phase signal of a signal on the second node; a fifth transistor supplying the first power supply voltage upon turning on in response to the signal on the first node; and a sixth transistor supplying the second power supply voltage upon turning on in response to the signal on the second node.

Abstract: A digital-to-analog conversion circuit includes a differential amplifier outputting 2N voltage levels dividing first and second voltages and a decoder distributing and supplying one of first and second voltages to a plurality of input terminals of the differential amplifier on the basis of digital data of N bits, and the differential amplifier includes 2K differential pairs including an inverting input terminal to which an output voltage is commonly input and a non-inverting input terminal to which one of voltages received by the plurality of input terminals is input and having output pairs commonly connected with each other and a tail current control circuit individually controlling current ratios of tail currents supplied to the differential pairs on the basis of a predetermined bit of digital data, in which N is equal to or greater than 3, and K is a positive number less than N.

Abstract: A display apparatus includes a plurality of source drivers outputting a gradation voltage signal and a selector switchably supplying the output gradation voltage signal to a plurality of data lines. The plurality of source drivers include a first source driver that has a first output buffer outputting a switching signal and a second source driver that has a second output buffer. The first output buffer has first and second transistors coupled via output terminals of the switching signal and turned ON and OFF complementarily. The second output buffer has third and fourth transistors coupled via output terminals of the switching signal and turned ON and OFF complementarily. The first and the second output buffers have the output terminals electrically coupled, and the first source driver has an abnormal detection circuit detecting a state causing a flow-through current to occur between the output terminals.

Abstract: A semiconductor device that outputs a reset signal for controlling a reset operation of a reset target circuit connected to a first power supply and a second power supply having a voltage lower than a voltage of the first power supply, the semiconductor device including: a power supply voltage monitoring circuit connected to the first power supply and the second power supply, the power supply voltage monitoring circuit monitors the voltage of the first power supply, wherein the power supply voltage monitoring circuit includes a first transistor having a first conductive type and a second transistor having a second conductive type different from the first conductive type, and wherein the reset signal is switched when the voltage of the first power supply is equal to or greater than a sum of a threshold voltage of the first transistor, and a threshold voltage of the second transistor.

Abstract: A PWM control circuit is configured to control the operation of an external circuit, and stop operations upon input of an anomaly detection signal from an externally provided anomaly detection circuit. A voltage detection circuit is configured to detect a change in the voltage value of a power source voltage and generate and output a hardware reset signal. A reset circuit outputs a reset signal to reset an entire device if the hardware reset signal from the voltage detection circuit, a software reset signal from a CPU, or the anomaly detection signal becomes active.

Abstract: A semiconductor device includes: a first semiconductor chip including a first internal circuit, first flip-flop circuits connected to the first internal circuit, first selectors, and first electrodes connected to an output of the first selector; first connection conductors; and a second semiconductor chip including second electrodes connected to the first electrode via the first connection conductor and a second internal circuit connected to at least one second electrode. At least one of the first and second semiconductor chips includes a test circuit. The test circuit includes a first detection circuit receiving a signal from each second electrode, a first selector control circuit controlling the selection of the first selector, and an expected value generation circuit. Each first selector includes a signal input receiving a signal from at least one first flip-flop circuit and an expected value input receiving an expected value signal from the expected value generation circuit.

Abstract: The disclosure includes a differential amplifier generating a difference voltage representing a difference between a reference voltage and a divided voltage obtained by dividing an inter-terminal voltage between a first and second terminals, a first transistor having a drain and a source connected to the first terminal and the second terminal, a voltage detection unit generating a detection voltage having a voltage value corresponding to the inter-terminal voltage, and a selection unit supplying one of the difference voltage and the detection voltage to a gate of the first transistor based on the inter-terminal voltage.

Abstract: The transmission abnormality detecting circuit provided in a receiving circuit receiving encoded data and configured to detect an abnormality of data transmission between a transmitting circuit and the receiving circuit includes: a decoding circuit configured to decode reception data received by the receiving circuit and to generate decoded data; an encoding circuit configured to encode the decoded data and to generate re-encoded data; and an error detecting circuit configured to detect whether an abnormality has occurred in data transmission between the transmitting circuit and the receiving circuit by comparing the reception data with the re-encoded data.

Abstract: A display device includes a display controller and a plurality of source drivers that supply gradation voltage signals to a plurality of pixel parts in a display panel. The plurality of source drivers each includes a setting register that stores setting data, at least one calculation circuit that performs calculation based on the setting data and calculates a setting value for a gradation voltage signal to be outputted, a source output unit that outputs a gradation voltage signal based on a video data signal and the setting value, and a code value calculation unit that calculates an error detection code value based on the calculation result of the calculation circuit. The display controller detects failure that has occurred in the calculation circuit in the plurality of source drivers, based on a calculation result of the code value in each of the plurality of source drivers.

Abstract: A differential amplifier includes a first input terminal, second input terminals, output terminals, differential amplification circuits, and a current source circuit. The first input terminal is one of an inverting input terminal and a non-inverting input terminal. Each of the second input terminals is another of the inverting input terminal and the non-inverting input terminal. The output terminals output voltages respectively corresponding to the second input terminals. The differential amplification circuits are connected to the first input terminal and the second input terminals and are provided corresponding to the second input terminals. The current source circuit is connected to the differential amplification circuits. Each of the differential amplification circuits outputs an output voltage corresponding to a combination of a voltage inputted to the first input terminal and a voltage inputted to one of the second input terminals from a corresponding one of the output terminals.