Abstract: An output amplifier circuit, and a display driver and a display device including the output amplifier circuit. The output amplifier circuit includes: first to nth amplifiers which receive first to nth input voltages and generate first to nth output voltages by amplifying the respective first to nth input voltages; first to Kth bias circuits which are provided corresponding to each of first to Kth amplifier groups formed by grouping the first to nth amplifiers into K groups, and each generates a bias voltage for setting a current value of an operating current of the amplifiers; first to Kth wirings which supply the bias voltage generated by each of the first to Kth bias circuits to the first to Kth amplifier groups respectively; and a switch circuit which, when in an ON state, connects one wiring among the first to Kth wirings with another wiring different from the one wiring.

Abstract: A digital-to-analog conversion device includes a Gray code conversion circuit receiving a series of digital data pieces including binary codes, and generating Gray code data pieces obtained by respectively converting the digital data pieces into Gray codes; a decoder receiving the Gray code data pieces and a plurality of reference voltages having different voltage values, selecting two reference voltages including an overlap from the plurality of reference voltages based on the Gray code data pieces, and outputting the two reference voltages as a first selection voltage and a second selection voltage, respectively; and an amplifier circuit including first and second input terminals that respectively receive the first selection voltage and the second selection voltage, and generating an output voltage by amplifying a voltage obtained by interpolating the first selection voltage and the second selection voltage by a weighting ratio assigned to the first and second input terminals.

Abstract: A video signal transmission device including: an imaging device that is an imaging device including pixels of plural colors arrayed in the same line, and that outputs RAW data generated by performing imaging; a conversion section that takes the RAW data output from the imaging device and rearranges pixel data such that pixel data of the same color is contiguous for each set of plural lines of a first direction; a digital-to-analog conversion section that converts digital data that has been converted by the conversion section into an analogue signal; and a transmission section that transmits the analogue signal that has been converted by the digital-to-analog conversion section.

Abstract: A flash memory is a memory element that stores a trimming code for adjusting a resistance value of a trimming resistor so that an oscillation frequency of an output clock signal generated by a CR oscillator circuit becomes a preset frequency. The CR oscillator circuit generates the output clock signal having a frequency based on a time constant determined by a resistance value of the trimming resistor being a resistive element, and a capacitance value of a capacitive element. An up-down counter is a counter circuit that, in synchronization with the output clock signal generated by the CR oscillator circuit, increases or decreases the trimming code stored in the flash memory, and outputs the trimming code as a trimming code for adjusting the resistance value of the trimming resistor.

Abstract: A multi-die module includes: a first semiconductor die having an internal line, an external electrode, and multiple internal electrodes and including a first control circuit that control a DC-DC converter; a second semiconductor die having multiple internal electrodes and including a second control circuit that controls a linear regulator; and a package that supports the first and second semiconductor dies. The second control circuit includes a voltage comparison circuit having a feedback input, a reference input, and a comparison output. In each of the first and second semiconductor dies, the multiple internal electrodes includes a first internal electrode. The feedback input of the voltage comparison circuit is connected to the first internal electrode of the second semiconductor die, which is connected to the first internal electrode of the first semiconductor die. The internal line connects the first internal electrode of the first semiconductor die to the external electrode.

Abstract: An output image adjustment device comprises: a projection unit that projects, on a projection target, a calibration image including groups of points representing coordinates in a first direction and a second direction intersecting the first direction, each of the points having a same type of color as a point adjacent in the first direction and a different type of color from a point adjacent in the second direction; an imaging unit that captures the calibration image projected on the projection target; and an image adjustment unit that adjusts coordinates of a calibrated image to be projected by the projection unit based on captured image data captured by the imaging unit.

Abstract: A clock error detection circuit which includes a cycle signal generation circuit that generates a cycle signal that reverses a level thereof at a start of each one cycle of a subject clock signal, a delay circuit that delays the cycle signal by a time shorter or a time longer than a prescribed cycle for the subject clock signal to output a delayed signal of the cycle signal, a holding circuit that holds a level of the delayed signal at the start of each one cycle of the subject clock signal to generate a hold signal, and a determination circuit that determines whether the level of the cycle signal matches the level of the hold signal to generate a result of the determination.

Abstract: A display device includes a video data signal output portion including a gamma setting data generation portion that generates gamma setting data, which is setting information for gamma correction corresponding to at least one partial area of a display screen of the display panel, based on the video data. The source driver includes: a gamma curve generation portion, configured to receive the gamma setting data and generate a local gamma correction curve, which is a gamma correction curve corresponding to the at least one partial area, based on the gamma setting data; a decoder portion, configured to perform gamma correction of gradation voltages corresponding to the plurality of pixel data fragments for each of the at least one partial area based on the local gamma correction curve; and an output portion, configured to output the pixel driving voltage based on the gradation voltages that have undergone the gamma correction.

Abstract: A charge pump circuit includes: first and second capacitors; a first switch element group turned on and off by a first clock signal and connecting a first voltage supply line and the first capacitor when turned on; a second switch element group turned on and off by the first clock signal and connecting a second voltage supply line and the second capacitor when turned on; and a third switch element group turned on and off by a second clock signal and connecting a voltage output line and the first and second capacitors when turned on. A control circuit controls a timing of a signal change of a first enable signal so that the signal levels of the first and second clock signals are fixed when the first and second switch element groups change from off to on, in response to stopping oscillating the first and second clock signals.

Abstract: An abnormal condition detection system includes a voice abnormality detector that includes a normal time model generator for generating a model of normal time voice data of a person riding in a vehicle as a normal time model based on voice data including voice of the person, and detects an abnormality in the voice based on a current voice data of the person and the normal time model; a vehicle body abnormality detector that detects an abnormality in a vehicle body of the vehicle based on acceleration data of the vehicle; and an abnormal condition determiner that determines whether or not the vehicle is in an abnormal condition based on a detection result of the voice abnormality detector and a detection result of the vehicle body abnormality detector.

Abstract: A level shifter includes: an input stage circuit receiving a relatively low level input signal, and an output stage circuit converting the input signal into a relatively high level signal and outputting the signal. The output stage circuit includes: first and second transistors, to which complementary signals generated according to the input signal are respectively input; a first switch circuit, having a main path connected with the first transistor, entering an ON-state with the second transistor entering the ON-state, and entering an OFF-state with the second transistor entering the OFF-state; and a second switch circuit, having a main path connected with the second transistor, entering the ON-state with the first transistor entering the ON-state, and entering the OFF-state with the first transistor entering the OFF-state. Regarding ON-resistance, the first switch circuit is greater than the first transistor, and the second switch circuit is greater than the second transistor.

Abstract: The disclosure includes: a first transistor, supplying a first power voltage to the output terminal when becoming ON according to a voltage of the input signal received by a gate; a second transistor, supplying a second power voltage to the output terminal in a case of becoming ON in accordance with the voltage of the input signal received by a gate; and an output control part, transitioning to ON by changing a voltage of the gate of the transistor in OFF between the first and second transistors at a change speed based on a current value of a bias current generated by a bias part when the voltage of the input signal changes. According to a voltage change of the input signal, the bias part sets a bias current value to a first value throughout a predetermined period, and switches to a second, lower value in other periods.

Abstract: A data transfer device includes: a video transmission circuit 24, transmitting video data from a first device 10 to a second device 50 during a video period as a timing of transmitting the video data; a transmission part 32, 72, transmitting non-video data between the first device 10 and the second device 50 during a video blanking period as a timing of transmitting the non-video data; and a monitoring part 30, 70, during the video blanking period, controlling the transmission part 32, 72 to stop transmission of the non-video data from the second device 50 to the first device 10 in response to presence of a signal from the first device 10 and stop transmission of the non-video data from the first device 10 to the second device 50 in response to presence of a signal from the second device 50.

Abstract: An output driver according to the disclosure includes a differential signaling circuit that includes a first transistor that generates a bias current, first and second nodes, and a resistor circuit connected between the first and second nodes, and outputs voltages respectively at the first and second nodes as a pair of differential signals by supplying the bias current to one of the first and second nodes based on a level of the input signals, a differential voltage circuit that supplies a differential voltage representing a difference between a center voltage of voltages between the first node and the second node and a predetermined reference voltage to a gate of the first transistor; and a pre-emphasis circuit that executes a pre-emphasis processing in response to changes in the level of the input signal, generating a current based on the differential voltage and adding it to the bias current.

Abstract: A display device includes a display panel, a gate driver; a source driver, supplying gradation voltage signals to multiple pixel parts via multiple data lines based on a video data signal, and supplying to the gate driver a gate control signal; and a video data transmission part, transmitting the video data signal to the source driver by using LVDS. The video data transmission part assigns, to an empty region that is a region other than regions assigned to multiple pixel data pieces forming one pixel of the video data signal in each data packet defined for a time of transmitting the video data signal for one pixel by using LVDS, an arithmetic value calculated based on the pixel data pieces, and transmits to the source driver together with the pixel data pieces as the video data signal.

Abstract: A semiconductor device includes a gradation voltage generation circuit, output amplifier circuits, a drive control circuit, and a delay time measurement circuit. The gradation voltage generation circuit converts, according to a load signal, pixel data pieces into gradation voltages and outputs the gradation voltages. The output amplifier circuits generate drive signals by individually amplifying the gradation voltages, and output the drive signals to data lines. The drive control circuit outputs the load signal to the gradation voltage generation circuit according to a horizontal synchronization signal. The delay time measurement circuit obtains, as a measured delay time, a time from receiving the measurement start signal until a voltage value of the drive signal outputted from one of the output amplifier circuits exceeds a predetermined threshold voltage. The drive control circuit shifts a timing of outputting the load signal by a difference between the measured delay time and a reference delay time.

Abstract: A digital-to-analog converter for effectively performing offset cancellation driving to reduce output variations includes: a decoder receiving a K-bit digital data signal and first and second voltages and generating 2K voltages each indicating the first or second voltage according to the digital data signal; and a differential amplifier outputting an output voltage having one of 2K voltage levels obtained by dividing the voltage between the first and second voltages into 2K voltage levels. The differential amplifier includes a MUX receiving 2K voltages, 2K differential pairs, and an amplification stage to which outputs of the 2K differential pairs are supplied. The MUX performs voltage supply to input terminals of each differential pair to actively cause that, in each differential pair, the input voltage to one input terminal in a first state differs from the input voltage to the other input terminal in a subsequent second state.

Abstract: It is an object to provide a video processing device and a video processing system capable of synthesizing a plurality of videos and displaying the synthesized video on a single screen in a form according to a request of a user. The disclosure includes a synthesis processing unit that generates a synthetic video signal by rendering a first video included in a designated region in a screen transparent and synthesizing the first video and a second video in a manner in which the first video based on a first video signal is arranged in the screen and the second video based on a second video signal different from the first video signal is arranged in the screen, and a memory that stores transparency control data for specifying the designated region and indicating a transparency aspect of the first video in the designated region.

Abstract: A semiconductor integrated circuit includes a first control part included in a first region in which a first operation speed is permitted, a second control part included in a second region in which power supply is cut off in a power saving mode and in which an operation at a speed higher than the first operation speed is required, a functional part having a specific function, and a selection part selecting either a first path connecting the first control part and the functional part or a second path connecting the second control part and the functional part in response to a control signal.

Abstract: The disclosure includes a memory, a horizontal synchronization detection circuit, a phase comparator, a lock circuit, a PLL, and a frequency divider. The memory that reads out a written video signal in response to a read clock signal and outputs it as an output video signal. The horizontal synchronization detection circuit detects a horizontal synchronization signal from the video signal. The phase comparator generates a phase difference signal indicating a phase difference between the horizontal synchronization signal and a frequency-divided clock signal. The lock circuit receives a free-running clock signal and generates a reference clock signal in which a phase signal is shifted by an amount of the phase difference indicated by the phase difference signal. The PLL generates the read clock signal that is locked to the phase of the reference clock signal. The frequency divider generates the frequency-divided clock signal by dividing the read clock signal.