Abstract: A video processing device includes: a frame number generating unit that generates frame numbers representing respective frames to which successively supplied video data belongs, the frame numbers differing between one frame and a next frame; a writing unit that writes a data block including a piece of the video data and the frame number corresponding thereto in a frame memory for every frame; a reading unit that reads out the data block written in the frame memory in the order of frames; and a video freezing determination unit that generates an abnormality determination signal that indicates video freezing when a current value of the frame number of the data block read stays the same as a previous value over a prescribed number of times.

Abstract: An electrostatic breakdown protection circuit and a capacitance sensor device are provided. An electrostatic breakdown protection circuit included in an electronic device including an external terminal and an internal circuit connected to the external terminal includes: a first series diode group in which n diodes including a first diode having an anode connected to the external terminal and a second diode having a cathode applied with a power supply voltage are connected in series; and a second series diode group in which n diodes including a third diode having a cathode connected to the external terminal and a fourth diode having an anode applied with a ground voltage are connected in series.

Abstract: A ladder resistor circuit includes a ladder resistor including first to k-th resistors connected in series and outputting a plurality of voltages by receiving a first potential and a second potential, a first correction resistor that has a resistance value equal to a series total resistance value of a resistor group constituted of first to r-th resistors among the first to k-th resistors, a second correction resistor that has a resistance value equal to a series total resistance value of a resistor group constituted of (r+1)-th to k-th resistors, and an amplifier that receives a potential of a connection point between the first and second correction resistors at an input terminal thereof, and has an output terminal thereof connected to a connection point between the r-th and (r+1)-th resistors.

Abstract: A display driver includes an amplifier circuit that outputs an output current based on a differential signal indicating a difference between a gradation voltage corresponding to a video signal and an output voltage to a source line of a display panel, thereby supplying the output voltage to the source line. An output current detection circuit generates a mirror current by copying the output current, and outputs an output current detection signal representing the mirror current. A failure determination circuit determines whether a failure is occurring or has occurred in the source line or not by comparing the level of the output current detection signal with a prescribed threshold value. The output current detection circuit includes a transistor that generates a mirror current by receiving the differential signal at a gate thereof, and a variable resistance that generates an output current detection signal upon receiving the generated mirror current.

Abstract: A semiconductor device, includes: a first inverter that operates on a first supply voltage and includes a transistor with a first polarity and a transistor with a second polarity different from the first polarity; a first inverter array that is connected to a gate of the transistor with the first polarity, includes a predetermined plural number of inverters connected in series, and operates on the first supply voltage; and a second inverter array that is connected to a gate of the transistor with the second polarity and includes inverters of the predetermined plural number connected in series, wherein a first stage inverter in the second inverter array operates on a second supply voltage that is higher than the first supply voltage, and a subsequent stage inverter subsequent to the first stage inverter operates on the first supply voltage.

Abstract: A semiconductor device includes first to N-th voltage output circuits each outputting an output voltage and outputs a feedback voltage having a voltage value corresponding to the output voltage, and a differential circuit including first to N-th primary side transistors to which N feedback voltages are input and that individually flow first to N-th currents through a first node, a secondary side transistor that flows a reference current corresponding to a reference voltage through the first node, and a current mirror circuit as an active load. The current mirror circuit includes first to N-th primary side load transistors individually coupled in cascade to the first to N-th primary side transistors, a secondary side load transistor coupled in cascade to the secondary side transistor and generates a voltage at a connection point between the secondary side transistor and the secondary side load transistor as a control voltage.

Abstract: An interface circuit comprises a timing signal generating unit that generates a timing signal indicating a timing to switch between a data input period and a non-input period, a plurality of driver error detection circuits that detects an error in source drivers, a selector circuit that selects one of the driver error detection circuits in the non-input period and that outputs a driver error detection signal indicating an error detection result, an input error detection circuit that detects an input error of a data signal and outputs an input error detection signal indicating the result, an OR circuit that outputs an OR of the driver error detection signal and the input error detection signal, and a signal output unit connected to an output part of the OR circuit.

Abstract: In a first output mode, a signal in which a data pulse having a positive polarity voltage value appears in a predetermined cycle is output as a positive polarity gradation data signal, and a signal in which a data pulse having a negative polarity voltage value appears in the predetermined cycle with a phase different from the positive polarity gradation data signal is output as a negative polarity gradation data signal. In a second output mode, the above positive polarity gradation data signal is generated, and a signal in which a data pulse having a negative polarity voltage value appears in the predetermined cycle with the same phase as the positive polarity gradation data signal is output as the negative polarity gradation data signal. The first and second output modes are alternatively executed, and the output mode is switched within a predetermined period at intervals of the predetermined period.

Abstract: A control device and an electronic control device are provided. The control device according to the disclosure includes a CPU bus, first to Nth (N is an integer equal to or greater than 2) peripheral devices, respectively operating in accordance with an address sent out from a CPU or respectively operating in a case of receiving respectively corresponding first to Nth operation start signals, a memory that stores sequence information indicating a procedure of operating the first to Nth peripheral devices, and a sequencer circuit that supplies the first to Nth operation start signals to the corresponding peripheral devices in order according to the sequence information when the CPU is abnormal or a load amount of the CPU exceeds a predetermined threshold.

Abstract: A modulation module includes a first modulation circuit that, upon receiving input of first setting information including first information designating a modulation mode, outputs a prescribed auxiliary signal as a first output signal, but upon receiving input of second setting information including second information designating a different modulation mode from the first information, outputs a first modulation signal generated by subjecting an input signal to modulation processing based on the second setting information as the first output signal. The modulation module further includes a second modulation circuit that is configured to output, as a second output signal, a signal generated by combining a second modulation signal generated by modulation processing and the first output signal.

Abstract: A power reception device includes a power reception control circuit connected to respective terminals of a power reception coil and receiving power supply by a voltage generated between the respective terminals due to a magnetic field, a matching capacitor connected in parallel with the respective terminals of the power reception coil, and a switching element connected in series with the capacitor and connected to the power reception control circuit. The power reception control circuit includes: a detection unit that detects a change in the power reception control circuit in accordance with a change in intensity of a magnetic field received by the power reception coil; and a switch adjustment unit that adjusts a state of the switching element when the detection unit detects a change that is equal to or greater than a prescribed degree.

Abstract: In a semiconductor device 100, at least one of a first transistor and a second transistor that supply a second voltage in a step-down circuit stepping down a first voltage to the second voltage and outputting the second voltage from an output portion is configured such that the number of second contacts of a source electrode which is connected to a ground voltage or is supplied with the first voltage is larger than the number of first contacts connecting a diffusion layer and a first metal layer of a drain electrode connected to the output portion, and the number of second vias of the source electrode connected to the ground voltage or supplied with the first voltage is larger than the number of first vias connecting the first metal layer and a second metal layer of the drain electrode connected to the output portion.

Abstract: A power-on reset circuit 10 has: an enhancement-type PMOS transistor P1 whose source is connected to VDD and whose drain is connected to node VJG; a depletion-type NMOS transistor D1 whose drain is connected to the node VJG; a first resistor portion having resistors R1, R2 that are connected in series, and whose one end is connected to a source of the depletion-type NMOS transistor D1, and whose another end is connected to GND, and at which a region between the resistors R1, R2 is connected to a gate of the enhancement-type PMOS transistor P1; and an inverter whose input is connected to the node VJG, and that outputs a reset signal.

Abstract: The present invention includes a common voltage generation part, a reference gamma voltage generation part, a gamma compensation part, a gradation voltage generating circuit, and a DA conversion part. The common voltage generation part generates a common voltage by amplifying a reference common voltage and applies the common voltage to a common electrode of a display panel. The reference gamma voltage generation part generates reference gamma voltages. The gamma compensation part takes in a voltage of the common electrode as a feedback common voltage from the display panel and generates compensation reference gamma voltages in which voltage values of the respective reference gamma voltages are adjusted on the basis of a difference between the feedback common voltage and the reference common voltage. The gradation voltage generating circuit generates gradation voltages on the basis of the compensation reference gamma voltages.

Abstract: Provided is an output amplifier having: a push-pull output-stage formed by first and second output-stage transistors; and a detection circuit detecting an abnormal output current output by the output amplifier and including: a coupling circuit, generating first and second currents mirroring current flowing in the first output-stage transistor and third and fourth currents mirroring current flowing in the second output-stage transistor, coupling the first and third currents at a first output node, outputting a first voltage at the first output node, coupling the second and fourth currents at a second output node, and outputting a second voltage at the second output node; and a determination circuit, outputting a determination signal indicating normality of an output current based on the first and second voltages. The coupling circuit generates the first to fourth currents. In the reference state, the third current > the first current, the second current > the fourth current.

Abstract: A sound output device has a sound playback unit that outputs, at any volume, sounds generated by playing back sound data pieces respectively in a first channel and a second channel. The sound playback unit performs a sound change process such that if a travel state of a vehicle is in a first travel state, a sound generated by playing back a sound data piece corresponding to the first travel state is outputted to either one of the first channel and the second channel, and if the travel state of the vehicle changes from the first travel state to a second travel state, the volume of the sound outputted from the one channel is gradually reduced to zero, and a sound generated by playing back a sound data piece corresponding to the second travel state is outputted to another of the first channel and the second channel.

Abstract: A correction circuit including: a first selector and a second selector that each select and output either of a first input signal or a second input signal, the first input signal and the second input signal having phases that are orthogonal to one another; a first multiplier carrying out multiplication of an output of the first selector and a first coefficient; a second multiplier carrying out multiplication of an output of the second selector and a second coefficient; a first adder carrying out addition of the first input signal and a multiplication result of the first multiplier; and a second adder carrying out addition of the second input signal and a multiplication result of the second multiplier, wherein an addition result of the first adder and an addition result of the second adder are outputted from a first output terminal and a second output terminal, respectively.

Abstract: An electronic control apparatus according to the disclosure includes: a controller, controlling the peripheral machines at a time of a normal operation mode, and performing diagnosis on whether a failure occurs with respect to at least one of the peripheral machines at a time of a monitoring mode.

Abstract: A semiconductor storage device includes: a data writing unit that writes information data to each block of a memory device in accordance with a write command; a verification processing unit that reads the information data out of a destination block every time after the information data is written to that block, and detects the number of error bits in the read-out information data from each block; and a re-writing unit that writes the information data to a block differing from the destination block if the number of error bits exceeds a prescribed threshold.

Abstract: A clock synchronization circuit that includes a signal generation circuit configured to generate a first signal and a second signal by receiving a signal output under a first clock with two logic circuits that respectively operate under a second clock different from the first clock; and a synchronization circuit configured to receive the first signal, the second signal, and a synchronization enabling signal for adjusting phases of the first signal and the second signal, and control the phases of the first signal and the second signal using a first output result from a logical operation performed on the second signal and on a result of a logical operation with the first signal and the synchronization enabling signal, and using a second output result from a logical operation performed on the first signal and on a result of a logical operation with the second signal and the synchronization enabling signal.