Abstract: A source driver includes a latch unit sequentially retrieving a video data signal for each data row corresponding to each of a first to n th horizontal scanning lines of the display panel, an overdrive arithmetic circuit calculating an overdrive value of the drive voltage applied to the pixel portions on an N th line based on a comparison result of comparing the data row corresponding to the N th line among the first to n th horizontal scanning lines and the data row corresponding to an (N?1) th line and a distance to the N th line from the source driver, and a voltage output unit generating the drive voltage applied to the pixel portions on the N th line based on the data row corresponding to the N th line and the overdrive value to output to the source line.

Abstract: An oscillator circuit includes an amplifying unit and a first feedback resistor. The amplifying unit includes an inverter at an input stage being connected to the one end of a crystal resonator, an inverter at an output stage being connected to the other end of the crystal resonator, and a linear amplifier. The linear amplifier is connected between an output terminal of the inverter at the input stage and an input terminal of the inverter at the output stage. The linear amplifier includes at least one inverter and a second feedback resistor. The second feedback resistor is connected in parallel to the at least one inverter. The linear amplifier has a conductance with a magnitude larger than a conductance of the inverter at the input stage and equal to or less than a conductance of the inverter at the output stage.

Abstract: An operational amplifier has a first input terminal and an output terminal connected to a second input terminal of the operational amplifier, and output nodes connected to the source lines of a display panel. During a failure inspection mode, the connection between the output node and the output terminal of the operational amplifier included in another output circuit among one output circuit and the other output circuit is disconnected and the output node instead of the output terminal is connected to the second input terminal of the operational amplifier. A pair of source lines connected to the output nodes of the one output circuit and the other output circuit are linked to each other, and signals attained by acquiring and binarizing voltages outputted from the operational amplifier in the other output circuit as a monitor voltage at different timings are acquired as first and second failure determination signals.

Abstract: The present invention includes a plurality of wireless terminals that each transmit a data packet including an acquired information signal by a first wireless communication scheme, and a relay device that receives the data packet transmitted from the wireless terminal and transmits the received data packet by a second wireless communication scheme. Each of the wireless terminals includes a first wireless communication circuit that performs a wireless communication by the first wireless communication scheme, a second wireless communication circuit that performs a wireless communication by the second wireless communication scheme, and a control unit that determines whether a wireless channel of the second wireless communication scheme is in use or not, and causes the first wireless communication circuit to transmit the data packet including the information signal to the relay device when the wireless channel is determined to be unused.

Abstract: A source driver includes: a first gradation voltage generation unit generating a gradation voltage of a first polarity supplied to a pixel on a first source line; a first amplifier receiving the gradation voltage of the first polarity to an input end, amplifying it, and outputting a voltage from an output end; a second gradation voltage generation unit generating a gradation voltage of a second polarity opposite to the first polarity to be supplied to a pixel on a second source line provided in the vicinity of the first source line; a second amplifier receiving the gradation voltage of the second polarity to an input end, amplifying it, and outputting a voltage from an output end; and a voltage comparison unit comparing a voltage of the input end of the second amplifier with the voltage of the output end of the second amplifier and outputs a comparison result.

Abstract: A video processing device includes a receiver that successively receives input images, each having a prescribed overlapping image superimposed in one or more areas thereof, a compositing image generation unit that successively generates compositing images based on the external information, a video compositing unit that successively generates composite images, a compositing abnormality detection unit that determines whether one or more areas of the composite image have abnormality or not, a comparison unit that compares the one or more areas of the input image with those of the composite image to determine whether or not the respective areas match, if it is determined that the composite image have no abnormalities, and an output control unit that outputs the input image if it is determined that the respective areas match, and outputs the composite image when it is determined that the respective areas do not match.

Abstract: The disclosure provides an output circuit, a display driver including the output circuit and a display device. The disclosure includes a PMOS transistor switch that outputs a positive voltage signal from an output terminal when it is turned on, an NMOS transistor switch that outputs a negative voltage signal from the output terminal when it is turned on, and a voltage control circuit that supplies a voltage obtained by shifting the level of a voltage of a source or a drain when the PMOS transistor switch is turned on to a high potential side to a back gate of the PMOS transistor switch and supplies a voltage obtained by shifting the level of a voltage of a source or a drain when the NMOS transistor switch is turned on to a low potential side to a back gate of the NMOS transistor switch.

Abstract: An operational amplifier has a first input terminal and an output terminal connected to a second input terminal of the operational amplifier, and output nodes connected to the source lines of a display panel. During a failure inspection mode, the connection between the output node and the output terminal of the operational amplifier included in another output circuit among one output circuit and the other output circuit is disconnected and the output node instead of the output terminal is connected to the second input terminal of the operational amplifier. A pair of source lines connected to the output nodes of the one output circuit and the other output circuit are linked to each other, and signals attained by acquiring and binarizing voltages outputted from the operational amplifier in the other output circuit as a monitor voltage at different timings are acquired as first and second failure determination signals.

Abstract: A semiconductor device, includes: a first inverter that operates on a first supply voltage and includes a transistor with a first polarity and a transistor with a second polarity different from the first polarity; a first inverter array that is connected to a gate of the transistor with the first polarity, includes a predetermined plural number of inverters connected in series, and operates on the first supply voltage; and a second inverter array that is connected to a gate of the transistor with the second polarity and includes inverters of the predetermined plural number connected in series, wherein a first stage inverter in the second inverter array operates on a second supply voltage that is higher than the first supply voltage, and a subsequent stage inverter subsequent to the first stage inverter operates on the first supply voltage.

Abstract: A source driver is provided, including a first data receiving part that receives a serial data signal via the first transmission line, a selector that outputs a serial data signal from either the first transmission line or the second transmission line according to a switching signal, a second data receiving part that receives the serial data signal output from the selector, a first serial-parallel conversion circuit that serial-parallel converts the serial data signal received by the first data receiving part and outputs the converted signal as first parallel data, a second serial-parallel conversion circuit that serial-parallel converts the serial data signal received by the second data receiving part and outputs the converted signal as second parallel data, and a comparison circuit that compares the first parallel data with the second parallel data and outputs a comparison result when the selector outputs the serial data signal from the first transmission line.

Abstract: An interface circuit generates a timing signal indicating the timing at which to switch between a data input period and a non-input period, and outputs a second start pulse signal obtained by delaying a first start pulse signal. Anomaly detection circuits detect an anomaly that has occurred in source drivers, and a detection result selection circuit selects one of the anomaly detection circuits during the non-input period and outputs a detection result signal indicating detection results. A selector selectively outputs the second start pulse signal or the detection result signal on the basis of the timing signal.

Abstract: A head-up display installed in a movable body includes an image acquisition unit that acquires an image including a graphic, a vibration information acquisition unit that acquires vibration information indicating vibration of the moving body, an image correction unit that generates a corrected image by performing, on the image, a blurring correction for blurring a contour of the graphic in the image based on the vibration information, and a display unit that displays the corrected image in a space as a virtual image.

Abstract: The present invention includes a common voltage generation part, a reference gamma voltage generation part, a gamma compensation part, a gradation voltage generating circuit, and a DA conversion part. The common voltage generation part generates a common voltage by amplifying a reference common voltage and applies the common voltage to a common electrode of a display panel. The reference gamma voltage generation part generates reference gamma voltages. The gamma compensation part takes in a voltage of the common electrode as a feedback common voltage from the display panel and generates compensation reference gamma voltages in which voltage values of the respective reference gamma voltages are adjusted on the basis of a difference between the feedback common voltage and the reference common voltage. The gradation voltage generating circuit generates gradation voltages on the basis of the compensation reference gamma voltages.

Abstract: An output circuit includes a first switch that outputs a positive voltage signal received via a first node when in an ON state, a second switch that outputs a negative voltage signal received via a second node when in an ON state, third and fourth switches that set the first and second nodes to a reference power supply voltage when in an ON state, a first voltage follower circuit that supplies a voltage obtained by shifting a voltage of the positive voltage signal supplied to the first node to a negative side by a predetermined voltage difference to a gate of the first switch, and a second voltage follower circuit that supplies a voltage obtained by shifting a voltage of the negative voltage signal supplied to the second node to a positive side by a predetermined voltage difference to a gate of the second switch.

Abstract: A low noise amplifier includes a transistor that amplifies and outputs inputted signals, a buffer that propagates outputs of the transistor to a subsequent circuit, a variable current source that supplies a bias current to the transistor, and a variable resistor connected between a gate terminal of the transistor and a terminal of the transistor to which the variable current source is connected, wherein in a case in which the inputted signals do not pass through the low noise amplifier, the buffer blocks outputs of the transistor, and settings of the variable current source and the variable resistor differ from settings in a case in which the inputted signals pass through the low noise amplifier.

Abstract: An output circuit includes a first switch that outputs a positive voltage signal received via a first node when in an ON state, a second switch that outputs a negative voltage signal received via a second node when in an ON state, third and fourth switches that set the first and second nodes to a reference power supply voltage when in an ON state, a first follower circuit that generates, as a gate voltage, a voltage signal following and being in phase with a voltage signal of the first node through source follower operation and supplies the gate voltage to a gate of the first switch, and a second follower circuit that generates, as a gate voltage, a voltage signal following and being in phase with a voltage signal of the second node through source follower operation and supplies the gate voltage to a gate of the second switch.

Abstract: A semiconductor device comprises a control unit, a semiconductor memory, a reference capacitance unit, a determination capacitance unit, a calibration circuit configured to supply a selection signal to the reference capacitance unit to selectively connect capacitors to differing potentials, and a determination circuit configured to charge a capacitance of the reference capacitance unit, to charge a capacitance of the determination capacitance unit, and to attain a comparison result by comparing the differing potentials. The control unit is configured to control rewriting of the semiconductor memory on the basis of a determination result of the determination circuit.

Abstract: A non-volatile memory circuit includes: a first memory including a plurality of cells that store values by respectively having elements whose states change physically due to application of a voltage from an exterior, a second memory including a plurality of cells that store values by respectively having the elements, a detector that, at a time of reading from the first memory, judges a value stored in each of the cells by comparing a threshold value and current values from the plurality of cells and a judging circuit supplying current of a predetermined current value to the detector as the threshold value.

Abstract: The present invention includes first to j-th DA conversion circuits that are fixedly coupled to one of a plurality of gradation reference voltage generating circuits steadily generating respective gradation reference voltage groups according to gamma correction characteristics of color components different from one another, and select a gradation reference voltage corresponding to a pixel data piece among the gradation reference voltage group generated by the one of gradation reference voltage generating circuits to output the gradation reference voltage as a gradation voltage, an output unit that assigns the first to j-th gradation voltages to respective first to j-th driving voltage signals in a mode according to an output switching signal, and outputs the first to j-th driving voltage signals to the display panel, and an output control unit that generates the output switching signal to switch modes of assigning the first to j-th gradation voltages to the first to j-th driving voltage signals at every divis

Abstract: The disclosure includes: first level shift part generating a voltage signal by converting an input voltage signal into amplitude between first negative and positive polarity power supply voltages; second level shift part generating a first polarity voltage signal by converting the voltage signal into amplitude between a reference and the first positive polarity power supply voltage; third level shift part outputting a first-polarity high voltage signal by converting the first polarity voltage signal into amplitude between a higher second positive polarity power supply voltage and the reference; fourth level shift part generating a second polarity voltage signal by converting the voltage signal into amplitude between the reference and the first negative polarity power supply voltage; and fifth level shift part outputting a second-polarity high voltage signal by converting the second polarity voltage signal into amplitude between a lower second negative polarity power supply voltage and the reference.