Abstract: An integrated circuit of an embodiment may comprise synchronous logic, combinational logic, and clock circuitry to clock the synchronous logic through various states dependent on the combinational logic. The synchronous logic may comprise a plurality of master-slave registers. The combinational logic is configured to drive data inputs of the synchronous logic dependent on states established by the master-slave registers. The clock circuitry is configured to clock the master portion of the master-slave registers with a lag rendering of a clock signal and to clock the slave portion of the registers with a lead rendering of the clock signal. In a particular example, the circuitry may define a frequency divider of a complementary CMOS realization.

Abstract: Systems and methods are disclosed herein to provide improved techniques for loading of configuration memory cells in integrated circuits, such as programmable logic devices. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a non-volatile memory adapted to store a first bit, a second bit, and a plurality of configuration data; a plurality of configuration memory cells; and control logic adapted to determine based on values of the first and second bits whether to load the configuration data from the non-volatile memory into the configuration memory cells.

Abstract: Circuits and related methods are provided for buffering reference voltages from noise associated with output driver transistors. In one example, an output driver buffer circuit includes an output driver transistor adapted to adjust an output voltage of an output pad. The circuit also includes a pre-driver circuit connected to a gate of the output driver transistor. The pre-driver circuit is adapted to receive a reference voltage to control the output driver transistor. The pre-driver circuit includes a precharged capacitor, a first switch adapted to connect the capacitor to the gate, and a second switch adapted to connect the reference voltage to the gate. The second switch is adapted to operate following a time period after the capacitor is connected to the gate. The capacitor is adapted to buffer noise associated with the output driver transistor during the time period.

Abstract: Systems and methods are disclosed herein to provide improved electrostatic protection for electrical circuits. For example, in accordance with an embodiment of the present invention, an electrostatic protection device includes: a drain region formed in a substrate; a gate separated from the substrate by a gate oxide; and an isolation region formed in the substrate, the isolation region being adapted to isolate the gate oxide from a DC voltage coupled to the drain region.

Abstract: In one embodiment, an electronic switch selectively passes an input signal from an input node to an output node based on a switch-control signal. The bulk of at least one transistor in the switch is connected to either the input node or the output node. The switch has two series-connected PMOS transistors connected in parallel with an NMOS transistor. The bulk and source of the first PMOS transistor are connected to the input node, while the bulk and source of the second PMOS transistor are connected to the output node. First and second level shifters ensure that the gates of the first and second PMOS transistors track the voltages at the input and output nodes, respectively. This configuration improves the ability of the switch to receive input voltages outside of the switch's power supply range without adversely affecting operations of the switch.

Abstract: In one embodiment, a programmable logic device is provided that includes a memory having memory cells, each memory cell operable to store either a configuration bit or a RAM bit; a masking circuit operable to mask a RAM bit by providing a masking value for the masked RAM bit; an error detection circuit operable to process the configuration bits during operation of the programmable logic device using an error detection algorithm, the error detection circuit calculating a signature that includes configuration bits and masking values; and a comparator operable to compare the signature calculated by the error detection circuit with a correct signature.

Abstract: Systems and methods are disclosed herein to provide logic block slice architectures and programmable logic block architectures along with control logic architectures in accordance with embodiments of the present invention. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of programmable logic blocks and a plurality of logic block slices within each of the programmable logic blocks, with each of the logic block slices having at least a first and a second slice each having at least a first lookup table. At least one of the programmable logic blocks includes at least a first logic block slice, a second logic block slice, and a third logic block slice, with the first logic block slice being a logic block slice type different from the second logic block slice, and the third logic block slice being a logic block slice type different from the first and second logic block slices.

Abstract: In one embodiment of the invention, a programmable logic device such as an FPGA includes a programmable fabric; a JTAG interface operable to receive configuration data for programming the fabric; a SPI interface operable to receive and transmit configuration data for programming the fabric; and circuitry coupled to the JTAG and SPI interfaces. The circuitry is operable, without being configured, to transfer configuration data received at the JTAG interface to the SPI interface for transmission to an external device having a SPI interface, such as a serial flash memory.

Abstract: Systems and methods are disclosed herein to provide dual slice architectures and programmable logic block architectures along with control logic architectures in accordance with embodiments of the present invention. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of programmable logic blocks and a plurality of dual-slice logic blocks within each of the programmable logic blocks, wherein each dual-slice logic block includes a first and a second slice each having at least a first lookup table, with a first one of the dual-slice logic blocks of a logic block slice type different from a second one of the dual-slice logic blocks, and a third one of the dual-slice logic blocks of a logic block slice type different from the first and second dual-slice logic blocks.

Abstract: In one embodiment, a decompression circuit is provided for a data stream that includes code words representing compressed data and uncompressed data. The decompression circuit includes a translation circuit adapted to identify the code words in the data stream and to translate the identified code words into corresponding decompressed data words; and a shift register operable to serially shift in uncompressed data in the data stream and to shift in parallel the decompressed data words from the translation circuit.

Abstract: In accordance with one or more embodiments of the present invention, a system includes a phase-locked loop circuit that receives a reference signal and a feedback signal and provides an output signal. A control circuit also receives the reference signal and the feedback signal and provides a correction current for the phase-locked loop circuit to reduce a phase error of the output signal.

Abstract: Systems and methods are disclosed herein to provide logic block slice architectures and programmable logic block architectures along with control logic architectures in accordance with embodiments of the present invention. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of programmable logic blocks, with at least one of the programmable logic blocks having at least a first, a second, and a third logic block slice of different logic block slice types.

Abstract: Systems and methods are disclosed herein to provide an improved approach to the configuration of integrated circuits such as programmable logic devices (PLDs). For example, in accordance with one embodiment of the present invention, a PLD includes volatile memory adapted to store configuration data to configure the PLD for its intended function. The PLD further includes non-volatile memory adapted to store configuration data which is transferable to the volatile memory to configure the PLD for its intended function. The PLD further includes a serial peripheral interface (SPI) port adapted to receive configuration data from an external device for transfer into one of the volatile memory and the non-volatile memory.

Abstract: Systems and methods are disclosed herein for decoder applications. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a decoder that receives a plurality of input signals and partially decodes the input signals based on their true and complement values to provide a plurality of decoded signals. The decoded signals, for example, may be utilized to control a multiplexer.

Abstract: In one embodiment of the invention, a symbol rate detector includes a nonlinear device to receive a pass band signal, a component to apply a Fourier Transform to a signal provided by the filter, and logic to select a peak frequency component from results of applying the Fourier Transform and to apply the peak frequency component as a symbol rate of a base band signal corresponding to the pass band signal.

Abstract: A programmable logic device (PLD) such as a field programmable gate array (FPGA) has a power-down mode of operation that reduces power consumption during standby or idle periods for the PLD. In one embodiment of the invention, the PLD includes an internal power supply operable to provide power to PLD's programmable logic blocks. The internal power supply powers down the programmable logic blocks in response to the assertion of a power-down signal.

Abstract: Method and apparatus for the testing of embedded memories in integrated circuits such as programmable logic devices are disclosed. In conjunction with a partial BIST engine, an external tester provides the embedded memories with test vectors. The on-chip partial BIST engine retrieves the test vectors from the embedded memories and compares them to corresponding expected test vectors supplied by the external tester. Based upon the comparison, the on-chip partial BIST engine forms comparison results indicating whether the retrieved test vectors differ from the corresponding expected test vectors. For programmable logic devices, a full BIST engine may be configured in the integrated circuit for generating the test vectors on chip.

Abstract: Improved reconfiguration techniques are provided for programmable logic devices (PLDs). For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of logic blocks, a plurality of input/output blocks and corresponding input/output pins, and a plurality of configuration memory cells. The configuration memory cells are adapted to store configuration data for configuration of the logic blocks and the input/output blocks. A data port is adapted to provide a clock signal to and receive configuration data from an external memory. A plurality of circuits are adapted to hold the input/output pins in a known logic state during the configuration.

Abstract: Systems and methods are disclosed herein in accordance with one or more embodiments of the present invention to provide programmable logic devices with non-volatile memory and a variable amount of distributed memory (e.g., in a cost-effective manner). For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of input/output blocks providing an input/output interface for the programmable logic device and a first and second plurality of logic blocks providing programmable logic functions, with only the second plurality of logic blocks further adapted to provide random access memory functions. A routing structure programmably interconnects the input/output blocks and the first and second plurality of logic blocks.

Abstract: A zero-power electrically erasable and programmable memory cell is implemented in CMOS (complementary metal oxide semiconductor) technology. A P-channel sense transistor has a source coupled to a first voltage generator, and an N-channel sense transistor has a source coupled to a second voltage generator. The drains of the P-channel and N-channel sense transistors are coupled together to form an output of the memory cell, and the gates of the P-channel and N-channel sense transistor are coupled together to form a floating gate of the memory cell. In an example embodiment of the present invention, each of the first and second voltage generators are variable voltage generators that apply a positive voltage at the respective source of each of the P-channel and N-channel sense transistors during the erase operation and/or that apply a ground or negative voltage at the respective source of each of the P-channel and N-channel sense transistors during the program operation.