Abstract: Various techniques are described to test memory arrays of a programmable logic device (PLD). In one example, a PLD includes a first memory array. The PLD also includes a plurality of sense amplifiers adapted to read a plurality of data values stored by the first memory array and provide a plurality of data signals corresponding to the data values. The PLD further includes a test circuit adapted to test the first memory array. The test circuit is coupled with the sense amplifiers and adapted to compare the data signals with a test signal to provide a pass/fail signal. In addition, the PLD includes a second memory array. The PLD also includes a data shift register adapted to test the second memory array.

Abstract: Systems and methods are disclosed herein to provide analog-to-digital interface techniques. For example, in accordance with an embodiment of the present invention, an integrated circuit includes an offset cancellation circuit provides offset cancellation for input signal paths under control of at least a first clock signal. A comparator, coupled to the offset cancellation circuit, provides an output signal based on a comparison of input signals provided on the input signal paths. A register receives the output signal and provides the output signal to a digital circuit under control of a first control signal, wherein the at least first clock signal is synchronized to a clock signal of the digital circuit.

Abstract: Methods and devices are disclosed herein to provide improved techniques for securing configuration data stored in non-volatile memories of programmable logic devices. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a non-volatile memory adapted to store a plurality of configuration data. A plurality of security fuses are adapted to store a plurality of logic states. Control logic is adapted to selectively secure the configuration data within the non-volatile memory based on the logic states stored in the plurality of security fuses.

Abstract: Systems and methods are directed to verification of configuration data stored in memory cells. For example, in one embodiment, an integrated circuit such as a programmable logic device includes a plurality of non-volatile memory cells and a plurality of volatile memory cells adapted to receive and store data provided from the plurality of non-volatile memory cells. A comparator is adapted to compare stored data from the plurality of volatile memory cells with the data values of the plurality of non-volatile memory cells. Control circuitry is responsive to the comparator to control whether configuration data from the plurality of non-volatile memory cells is loaded to the plurality of volatile memory cells.

Abstract: Systems and methods are disclosed herein to provide improved jitter tolerant delay-locked loop circuitry. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a plurality of delay cells each having a plurality of programmable delay taps. Each delay cell is adapted to provide a delayed clock signal delayed by a selected number of the delay taps. A phase detector is adapted to compare a first clock signal with a selected one of the delayed clock signals to obtain a comparison result and provide a plurality of control signals in response to the comparison result. An arithmetic logic unit (ALU) is adapted to vary the selected number of delay taps in response to the control signals provided by the phase detector.

Abstract: In one embodiment of the invention, a bias signal monitor has two signal comparators that compare two (power supply) voltages at two different bias points and a logic circuit that processes the outputs from the two signal monitors to generate a bias signal monitor output signal. The logic circuit implements hysteresis-based processing such that (1) if both signal comparators are active (indicating that a first voltage is greater than the second voltage relative to both bias points), then the monitor output is active, (2) if both signal comparators are inactive (indicating that the first voltage is not greater than the second voltage relative to either bias point), then the monitor output is inactive, and (3) if one signal comparator is active and the other is inactive, then the monitor output keeps its previous value. This hysteresis characteristic prevents relatively small oscillations between the voltages from changing the monitor output.

Abstract: In one embodiment of the invention, a programmable level shifter can be selectively configured to operate in either a high-speed mode or a low-power mode. In both modes, the level shifter converts an input signal in one power supply domain into an output signal in another power supply domain. In the high-speed mode, p-type devices are configured as a current-mirror amplifier that provides the level shifter with relatively fast switching speed. In the low-power mode, the same p-type devices are configured as a cross-coupled latch that provides the level shifter with relatively low power consumption. Selectively enabled n-type devices provide the low-power mode with larger effective n-type devices to flip the cross-coupled latch formed by the p-type devices in the low-power mode.

Abstract: Systems and methods provide programmable logic block architectures and routing architectures for the programmable logic blocks. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of programmable logic blocks and a plurality of logic block slices within each of the programmable logic blocks. A first routing circuit provides global signal routing within the programmable logic device for the corresponding programmable logic block. A first input routing circuit receives signals from the first routing circuit and routes the signals to the logic block slices within the corresponding programmable logic block.

Abstract: In one embodiment, an output driver buffer circuit for a logic device includes an output driver transistor adapted to adjust an output voltage of an output pad; a capacitor adapted to be connected to the transistor gate and further adapted when charged and connected to the gate to turn the transistor on; and a reference voltage source adapted to be connected to the transistor gate and further adapted when connected to the gate to maintain the transistor on. The reference voltage source is further adapted to be connected to the transistor gate after the capacitor has turned the transistor on and independent of the level of the output voltage of the output pad.

Abstract: In one embodiment of the invention, a circuit may include and/or involve a correlator, a programmable fabric, and logic to enable selection of one of default processing logic and alternate processing logic to process corresponding data and coefficient values of the correlator.

Abstract: In one embodiment of the invention, a clock-and-data-recovery (CDR) system has a multi-phase clock generator that generates a plurality of phase-offset clock signals and one or more channel circuits, each receiving a (different) input data signal and all of the phase-offset clock signals and generates an output data stream and a recovered clock signal. Each channel circuit has a plurality of data registers (e.g., flip-flops), each receiving the input data signal at its clock input port and a different one of the phase-offset clock signals at its data input port, such that the flip-flop is triggered at each (rising) edge in the input data signal. The channel circuit processes the outputs from the different flip-flops to select an appropriate phase-offset clock signal for use in sampling the input data signal to generate the output data stream, where the recovered clock signal is generated from the selected phase-offset clock signal.

Abstract: Systems and methods are disclosed directed to techniques with respect to defective configuration memory cells. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of configuration memory cells; and at least one spare memory cell, wherein the at least one spare memory cell is adapted to store configuration data to provide to at least one defective configuration memory cell.

Abstract: In one embodiment, a programmable logic device for recovery from soft error upsets (SEUs) includes: a configuration memory operable to store configuration data; a configuration engine operable to configure the configuration memory; an error detection circuit operable to determine if the stored configuration data in the configuration memory has an error; and a configuration reset circuit operable to trigger the configuration engine to reconfigure the configuration memory if the error detection circuit detects the error.

Abstract: In one embodiment of the invention, a programmable logic device comprises configuration memory adapted to store configuration data and a plurality of programmable logic blocks. At least one programmable logic block includes a plurality of dual-slice logic blocks, each dual-slice logic block including first and second slices, each slice including at least two lookup tables (LUTs) and a register. The programmable logic block further includes control logic adapted for selecting control signals separately at a programmable block level, a dual-slice block level, and a register level, the control logic responsive to configuration data stored within the configuration memory.

Abstract: In one embodiment, a data decompression circuit for a data stream having a repeated data word is provided. The data stream is compressed into a series of data frames such that the repeated data word is removed from the series of data frames and such that each data frame corresponds to a header. The circuit includes a decompression engine configured to decompress each data frame into a corresponding decompressed data frame, the decompression engine being further configured to decode each header to identify whether word locations in the corresponding decompressed data frame should be filled with the repeated data word.

Abstract: In one embodiment, the invention can be a clock-generating circuit having one or more clock-processing circuits, each outputting a clock signal having an adjustable phase. Each clock-processing circuit comprises a divider and a divisor control circuit. Each divider divides an input clock signal by a respective divisor value and outputs a corresponding output clock signal whose period is determined by the divisor value and the period of the input clock signal. Each divider receives the respective divisor value from the corresponding divisor control circuit, wherein the divisor value is selected in order to achieve a desired frequency and phase for the corresponding output clock signal. Temporarily changing a divisor value can advance or delay the phase of the corresponding output clock signal without having to reset the divider.

Abstract: In one embodiment, an integrated circuit has configurable application circuitry that operates at any one of multiple available power supply voltages. PT-control circuitry, operating at a PT reference voltage, generates a PT-control signal indicative of variations in process and temperature. Application-control circuitry controls the configuration of the application circuitry based on the selected power supply voltage for the application circuitry and the PT-control signal, where the selected power supply voltage is independent of the PT reference voltage.

Abstract: In one embodiment, a programmable logic device (PLD) such as a field programmable gate array (FPGA) includes a non-volatile memory adapted to store a first bit, a second bit, and a plurality of configuration data. A plurality of configuration memory cells within the PLD is adapted to receive configuration data transferred from the non-volatile memory. The PLD further includes control logic adapted to determine based on the logic states of the first and second bits stored in the non-volatile memory and prior to any transfer of the configuration data whether to transfer the configuration data from the non-volatile memory to the configuration memory cells.

Abstract: Systems and methods are disclosed herein to provide high fan-out signal routing. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of logic blocks; an interconnect structure adapted to route signals among the logic blocks; and a secondary routing network adapted to route signals among the logic blocks. The secondary routing network may include a plurality of horizontal splines adapted to route signals within the programmable logic device; a plurality of vertical spline taps adapted to route signals within the programmable logic device; a plurality of common interface blocks adapted to route signals between the horizontal splines and the vertical spline taps; and a plurality of horizontal secondary branches adapted to route signals from the vertical spline taps to the logic blocks.

Abstract: In one embodiment of the invention, an integrated circuit, such as an FPGA, comprises a distributed FIFO architecture that supports data transfer from an external device, such as an SDRAM, via an interface that receives a non-continuous, asynchronous strobe clock and a data lane having a plurality of bit lines from the external device. The distributed FIFO architecture comprise a FIFO for each bit line and a FIFO controller. Under control of the FIFO controller, data is written into each FIFO using a FIFO write clock based on the strobe clock, while data is read out from each FIFO using a FIFO read clock based on a local reference clock of the integrated circuit. The distributed FIFO architecture is designed to handle a range of possible phase differences between the FIFO write and read clocks to safely convert from the asynchronous, non-continuous strobe domain to a local continuous clock domain.