Patents Assigned to Leader Electronics
  • Publication number: 20240121380
    Abstract: A resolution measurement method performed by a computer device for a camera comprises: generating a distortion map which represents a correspondence relation between coordinates of all pixels of a first test chart and coordinates of all pixels of the first test chart in an image captured by a camera which causes distortion in a photography field of view; generating, according to the correspondence relation represented by the distortion map, a distorted test chart which is a distorted image of a second test chart that is used for measuring resolution at a specific area in the first test chart in the captured image and performing, by using the distorted test chart, measurement of resolution according to a contrast method at a part, that corresponds to the specific area, in the photography field of view of the camera.
    Type: Application
    Filed: February 10, 2021
    Publication date: April 11, 2024
    Applicant: Leader Electronics Corp.
    Inventor: Kouichi TODA
  • Publication number: 20220394200
    Abstract: To generate training data based on normal content and anomalous content generated from the normal content. A training data generation method for generating training data used for generating a learned model for determining whether there is an anomaly in an inspection target, the training data generation method including: receiving normal content regarding the inspection target and anomalous content generated from the normal content; and generating training data based on a set of the normal content and one or more pieces of the anomalous content.
    Type: Application
    Filed: September 17, 2020
    Publication date: December 8, 2022
    Applicant: Leader Electronics Corp.
    Inventor: Xiaodong WANG
  • Patent number: 11355920
    Abstract: An improved electric circuit structure for short circuit protection is applicable to examining a device under test, comprising a circuit breaking element, a thermistor, a filtering and rectifying module and a capacitor. A first end of the circuit breaking element is connected to a power source. The filtering and rectifying module is connected to a second end of the circuit breaking element, a ground, a first end of the thermistor and a first end of the capacitor. A second end of the capacitor is connected to a second end of the thermistor. The capacitor is connected in parallel with the device under test. The circuit breaking element disclosed in the present invention is a ceramic tube fuse and forms an open circuit when the device under test forms a short circuit. Meanwhile, the ceramic tube fuse withstands voltage between its first and second end without generating any physical damage.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: June 7, 2022
    Assignee: Leader Electronics
    Inventors: Shi-Guo Deng, Zuo-Quan Zhou, Jing Feng
  • Patent number: 11108224
    Abstract: An improved electric circuit structure for short circuit protection is applicable to examining a device under test, comprising a circuit breaking element, a thermistor, a filtering and rectifying module and a capacitor. A first end of the circuit breaking element is electrically connected to a power source. A first end of the thermistor is electrically connected to a ground. The filtering and rectifying module is connected between the second end of the circuit breaking element and the second end of the thermistor. The capacitor is connected to the filtering and rectifying module and in parallel with the device under test. The circuit breaking element disclosed in the present invention is a multi-protector fuse and forms an open circuit when the device under test forms a short circuit. Meanwhile, the multi-protector fuse is able to withstand voltage between its first and second end without generating any physical damage.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: August 31, 2021
    Assignee: Leader Electronics Inc.
    Inventors: Shi-Guo Deng, Zuo-Quan Zhou, Jing Feng
  • Patent number: 9813699
    Abstract: A marker generating method is provided for facilitating the finding of positions which correspond to one another among a plurality of images associated with a video signal. A position within an image (800) associated with a video signal is selected, with a cursor (802, 804) to display a marker (812, 822-826) at a position corresponding to the selected position, in a different image (810, 820) associated with the video signal.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: November 7, 2017
    Assignee: Leader Electronics Corp.
    Inventors: Yuji Amino, Yoshihiro Sakamoto
  • Patent number: 9112326
    Abstract: A power adapter with a combinational plug has a plug assembly and a converter assembly. The converter assembly has two guide walls formed on a bottom surface thereof for a base of the plug assembly to be inserted therein, and at least one fixing member and a positioning boss formed on the base to engage at least one engagement slot and a positioning slot formed in the base. The base is mounted within the guide walls, the at least one fixing member engages the at least one engagement slot, and the positioning boss engages the positioning slot for the plug assembly and the converter assembly to be firmly combined. The locations of the positioning boss and the positioning slot are unique for each power adapter. Accordingly, a power adapter with low production cost and misuse protection can be provided.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: August 18, 2015
    Assignee: Leader Electronics Inc.
    Inventor: Feng-Rong Liu
  • Publication number: 20150146013
    Abstract: A marker generating method is provided for facilitating the finding of positions which correspond to one another among a plurality of images associated with a video signal. A position within an image (800) associated with a video signal is selected, with a cursor (802, 804) to display a marker (812, 822-826) at a position corresponding to the selected position, in a different image (810, 820) associated with the video signal.
    Type: Application
    Filed: May 18, 2012
    Publication date: May 28, 2015
    Applicant: Leader Electronics Corp.
    Inventors: Yuji Amino, Yoshihiro Sakamoto
  • Publication number: 20150064955
    Abstract: A power adapter with a combinational plug has a plug assembly and a converter assembly. The converter assembly has two guide walls formed on a bottom surface thereof for a base of the plug assembly to be inserted therein, and at least one fixing member and a positioning boss formed on the base to engage at least one engagement slot and a positioning slot formed in the base. The base is mounted within the guide walls, the at least one fixing member engages the at least one engagement slot, and the positioning boss engages the positioning slot for the plug assembly and the converter assembly to be firmly combined. The locations of the positioning boss and the positioning slot are unique for each power adapter. Accordingly, a power adapter with low production cost and misuse protection can be provided.
    Type: Application
    Filed: September 3, 2013
    Publication date: March 5, 2015
    Applicant: Leader Electronics Inc.
    Inventor: Feng-Rong Liu
  • Patent number: 8786995
    Abstract: A surge current suppressing circuit is applied between an AC power and an electronic device that receives the AC power via a first AC power line and a second AC power line. The surge current suppressing circuit has a first input fuse connected to the first AC power line, and a first air-core inductor connected in series with the first input fuse on the first AC power line to suppress a surge current. Depending upon the practical applications, the surge current suppressing circuit can further have a second air-core inductor connected to the second AC power line, a capacitor connected between the two AC power lines or both.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: July 22, 2014
    Assignee: Leader Electronics Inc.
    Inventors: René Frederik Koch, Min-Ta Hsiao, Ming-Cheng Chuang
  • Patent number: 8773067
    Abstract: A charging base has a bottom case, a printed circuit board (PCB) and a top case. The bottom case includes at least one drainage hole. The PCB is mounted in the bottom case and includes a mounting hole, a positioning block and charging terminals. The positioning block is attached to the PCB and has through holes. The charging terminals are secured to the positioning block and have apertures. The top case covers the bottom case and includes terminal holes and a top enclosed wall. The top enclosed wall is secured around the positioning block. Therefore, when water accidentally enters the charging base via the terminal holes, the water will sequentially flow through the apertures of the charging terminals, the through holes of the positioning block and the mounting hole of the PCB and subsequently drain out of the drainage hole of the bottom case.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: July 8, 2014
    Assignee: Leader Electronics Inc.
    Inventor: Kuan-Chih Chen
  • Publication number: 20140184907
    Abstract: A jitter-associated data generator is provided for generating data associated with jitter. The jitter-associated data generator comprises a first circuit, a second circuit, and a third circuit. The first circuit generates an output including frequency components in a first frequency band common to first and second jitter, from a received digital input, as digital data associated with first jitter. The second circuit generates an output including frequency components in a second frequency band corresponding to the difference between the first and second jitter, from the received input, as differential digital data. The third circuit generates an output including frequency components in a third frequency band including the first and second frequency bands, from the received first jitter-associated digital data and differential digital data, as digital data associated with the second jitter.
    Type: Application
    Filed: December 24, 2013
    Publication date: July 3, 2014
    Applicant: Leader Electronics Corp.
    Inventor: Kensuke Yoshida
  • Patent number: 8414318
    Abstract: A power adapter with a rotatable plug module has a body, a circuit module and a plug module. The body has multiple fasteners and multiple clasps. The fasteners are arranged in a ring shape. Each of the clasps is formed on one side of each fastener and extends from the fasteners in the same orientation. The circuit module has a circuit board mounted in the body. The plus module has multiple conducting blades and multiple holes. The holes are engaged with the fasteners of the substrate when the plug module is rotated to correspond to the fasteners. The conducting blades are electrically connected to the circuit board. Because the plug module is rotatable and can be removed from the body, the power adapter with suitable conducting pins is available to various sockets.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: April 9, 2013
    Assignee: Leader Electronics Inc.
    Inventor: Shen-Liang Chen
  • Patent number: 8279348
    Abstract: A display method and apparatus are provided for enabling a user, whether or not he has experience, to readily detect a luminance level of a video image with high accuracy. A luminance level of a video signal of a video image is converted to color information to display a change in the luminance of the video image as a change in color. The conversion preferably involves a method of converting the luminance level to color information of three primary colors, red, green, blue, in accordance with a plurality of weights, respectively, a method of converting a luminance level in a predetermined range to color information having a changing rate larger than a changing rate of the luminance level, a method of converting a luminance level out of the predetermined range to color information of a maximum or a minimum level, or the like. Also, the input video signal is preferably displayed together with a converted video image side by side or one on another.
    Type: Grant
    Filed: December 11, 2007
    Date of Patent: October 2, 2012
    Assignee: Leader Electronics Corporation
    Inventors: Koji Yano, Genichi Imamura
  • Patent number: 7946868
    Abstract: A power adapter having a replaceable and rotatable plug has a body having an annular chamber, two conducting elements inside the annular chamber, four channels recessed on a top thereof to communicate with the annular chamber, and an engagement slot abutting each of the four channels; and a hollow plug having two intermediate conducting elements, a cylinder protruding beyond a bottom of the plug and received in the annular chamber, four arced holes communicating with an inner portion of the plug, four engagement blocks protruding from a cylindrical periphery to respectively correspond to the four channels and four engagement slots, and at least two prongs mounted on a top thereof, one end of each of the two prongs penetrating through the plug to electrically connect with corresponding intermediate conducting elements. Given the aforementioned structure, the plug can be replaced and selectively oriented with respect to the body.
    Type: Grant
    Filed: November 19, 2009
    Date of Patent: May 24, 2011
    Assignee: Leader Electronics Inc.
    Inventor: Kuan-Chih Chen
  • Patent number: 7746674
    Abstract: A push-pull type self-oscillating power converter uses a main power transformer connected to a current transformer in series in such a way that a secondary current flowing through secondary sides of the two transformers is feedback to the primary side of the current drive transformer to generate a drive current for driving two switches. The drive current is proportional to the secondary current in the secondary side of the main power transformer.
    Type: Grant
    Filed: July 30, 2007
    Date of Patent: June 29, 2010
    Assignee: Leader Electronics Inc.
    Inventor: René Frederik Koch
  • Patent number: 7714935
    Abstract: A highly integrated data structure for synthesizing a waveform is provided for facilitating integrated handling of the data. The data structure for waveform synthesis data or use in generation of a target waveform comprises, at a macro level, a macro waveform value data field for storing a waveform value data section including source waveform value data for use in the generation of the target waveform, and a macro (first) header including control data for forming a macro waveform in the target waveform using the source waveform value data included in the data field. At a micro level, the data structure according to the present invention comprises a micro waveform value data field, and a micro (second) header for generating a micro waveform in the target waveform using the waveform value data included in the micro waveform value data field.
    Type: Grant
    Filed: May 29, 2003
    Date of Patent: May 11, 2010
    Assignee: Leader Electronics Corporation
    Inventor: Tomomi Hara
  • Patent number: 7663698
    Abstract: A genlock device comprises: means (31) for inputting an external reference signal; means (32,33,34,36,39,40,41,42,44) for generating a master reference clock signal synchronized in phase with the external reference signal; and means (37) for storing a genlock state. The genlock state includes, for example, absence of a synchronization signal in the external reference signal. The genlock device can further comprise: means (45) for storing a voltage value determined so that a voltage controlled oscillator (40) oscillates a signal having a frequency higher or lower by a predetermined value than a reference frequency of the voltage controlled oscillator; and means (44) for judging whether a voltage value which controls the voltage controlled oscillator is larger or smaller than the voltage value.
    Type: Grant
    Filed: January 17, 2006
    Date of Patent: February 16, 2010
    Assignee: Leader Electronics Corporation
    Inventor: Tomomi Hara
  • Patent number: 7577191
    Abstract: An apparatus comprises input means, detection means and a selector, and automatically detects a kind of serial signal used in BER measurement. The input means receives at least two signals which include a data signal, and a clock signal having a period corresponding to one bit of the data signal. The detection means determines which one of the at least two signals is a clock signal or a data signal. The selector outputs the signal determined to be a clock signal from a clock signal terminal and outputs the signal determined to be a data signal from a data signal terminal.
    Type: Grant
    Filed: December 12, 2005
    Date of Patent: August 18, 2009
    Assignee: Leader Electronics Corporation
    Inventors: Akira Yasumoto, Susumu Akada, Minoru Nishiyama
  • Patent number: 7535487
    Abstract: A measuring instrument is fed with a video output signal, and performs RGB processing on the video output signal to generate graphic data. A video signal level in the graphic data is measured and video signal level data is generated. Display data including the graphic data and the video signal level data is generated. A display device receives display data from the measuring instrument. The display data is visualized and an image and a video signal level are displayed.
    Type: Grant
    Filed: October 19, 2007
    Date of Patent: May 19, 2009
    Assignee: Leader Electronics Corporation
    Inventors: Genichi Imamura, Masaaki Nagai, Takayuki Miyajiri
  • Patent number: 7529321
    Abstract: A digital satellite broadcast receiver capable of an optimum signal reception even when an arbitrary outdoor unit is connected. Please noise characteristics of an outdoor unit connected to a digital satellite broadcast receiver when receiving a burst symbol is estimated based on a bit error rate of an 8PSK modulation signal determined by a trellis decoder (7) when a CNR measured by a CNR measurement circuit (5) is equal to a preset value, and, based on the estimated phase noise characteristics of the outdoor unit, a filter factor of a loop filter (9) inserted into a carrier regenerative loop is set.
    Type: Grant
    Filed: September 17, 1999
    Date of Patent: May 5, 2009
    Assignees: Kabushiki Kaisha Kenwood, Leader Electronics Corporation
    Inventors: Kenichi Shiraishi, Shoichi Suzuki, Akihiro Horii, Shoji Matsuda, Takahiro Wada