Abstract: A measuring instrument 50 comprises: a) means which is fed with a video output signal, and performs RGB processing on the video output signal to generate graphic data; b) means for measuring a video signal level in the graphic data, and generating video signal level data; and c) means for generating display data including the graphic data and the video signal level data. A display device 10 comprises: a) means for receiving the display data from the measuring instrument 50; and b) means for visualizing the display data and displaying an image and a video signal level.

Abstract: A phase shifter (70) for correcting the phase of a sub-carrier signal input into a decoder to a burst signal has a phase shift setting (5), a correction amount setting (9?), a phase shifter (6) and a 90-degree phase shifter (7). The phase shift setting (5) holds a phase shift amount for all the scanning lines. The correction amount setting (9?) holds a correction phase shift amount for every part of all the scanning lines. The phase shifter (6) partially shifts the phase of the sub-carrier signal in a unit of part of all the scanning lines, and shifts it in a unit of all the scanning lines, based on said phase shift amount and said correction phase shift amount. The 90-degree phase shifter (7) generates a sub-carrier signal orthogonal to said phase shifted sub-carrier signal.

Abstract: A video signal level monitoring apparatus which monitors the level of a video signal, said apparatus comprises means for inputting a first color difference component (Cb) and a second color difference component (Cr) of a component video signal, means for inputting a luminance component (Y) of the component video signal as a luminance component (Y) of a composite video signal, means for generating a color component (C) of the composite video signal from the first color difference component and the second color difference component, and means for displaying each of the amplitude values of the color component (C) and the luminance component (Y) in a one-dimensional direction. Preferably, the display means displays each amplitude value in a bar graph display and scale marks corresponding to a minimum acceptable value and a maximum acceptable value within a range in accordance with a predetermined standard.

Abstract: A measuring instrument is fed with a video output signal, and performs RGB processing on the video output signal to generate graphic data. A video signal level in the graphic data is measured and video signal level data is generated. Display data including the graphic data and the video signal level data is generated. A display device receives display data from the measuring instrument. The display data is visualized and an image and a video signal level are displayed.

Abstract: An external synchronous signal circuit comprises: means for measuring a phase difference between the external frame synchronous signal (FRM_SYNC) and the frame synchronous signal (FRM) of the digital video signal; means for generating a signal (EXT_H) having the same period as that of the horizontal synchronous signal (HBK) of the digital video signal, the signal (EXT_H) having the measured phase difference with reference to the frame synchronous signal (FRM) of the digital video; and means for generating a signal (EXT_F) having the same period as that of the frame synchronous signal (FRM) of the digital video signal, the signal (EXT_F) having the measured phase difference with reference to the frame synchronous signal (FRM) of the digital video. The generated signals (EXT_F) and (EXT_H) are outputted as an external frame timing signal and an external horizontal timing signal of an external synchronous signal.

Abstract: A frame signal phase adjuster comprises units for inputting a parallel clock and a reference signal (22-4 and 22-1); generating a frame signal from the reference signal (22-1), adjusting a phase of the frame signal (22-3), generating an adjusted frame signal synchronized by the parallel clock from the parallel clock and the adjusted frame signal (22-4), generating a frame reset pulse signal based on the parallel clock and the adjusted frame signal synchronized by the parallel clock (22-2), and outputting the frame reset pulse signal (22-2). The unit (22-4) adjusts the phase of the frame signal so that the frame signal is constantly HIGH or LOW throughout a setup time and a hold time.

Abstract: A jitter canceling apparatus is provided for canceling jitter in a video signal. For processing a video signal, using as a reference an internal synchronization signal and an external synchronization signal different from the internal synchronization signal in the jitter canceling apparatus, an external synchronization signal generator generates the external synchronization signal from an external reference signal. A jitter detector detects time difference jitter, which is jitter in a time difference between the internal and external synchronization signals. The external synchronization signal generator controls the external synchronization signal generating operation in response to the detected time difference jitter to reduce the time difference jitter.

Abstract: A vector waveform rotation device (60) for rotating a vector waveform displayed on a vector comprises rotation amount setting means (5?) for holding a rotation amount ?, and means (6?) for inputting a first color difference signal (B-Y signal) and a second color difference signal (R-Y signal) demodulated from a chrominance signal of a composite video signal as x and y, and rotating a vector (x, y) by generating a vector (x?,y?)=(x·cos ??y·sin ?, x·sin ?+y·cos ?) from the vector (x,y)=(first color difference signal, second color difference signal).

Abstract: A vector waveform correction device corrects a vector waveform displayed on a vector scope. A first color difference signal and a second color difference signal demodulated from a chrominance signal of a composite video signal are input as x and y, and a vector (x, y) is partially rotated in a unit of part of all the scanning lines.

Abstract: The transformer has a pair of cores, a winding assembly, a primary coil and a secondary coil. Each core has a center and an elliptical central core formed at the center. The winding assembly has a body and two mounting brackets. The body is a hollow elliptical column with two ends and has an outer surface and an elliptical mounting hole. The two mounting brackets are attached respectively to the two ends of the body, and each mounting bracket has a slot with a rounded edge and multiple pins. Since the central cores are elliptic, each central core may have a larger volume, such that the transformer may have a greater heat-absorbing capability, so transformer temperature rises slower. Furthermore, the winding assembly mounted on the central core is more stable, and even if the pins detach, the winding assembly will remain in position.

Abstract: A multi-phase signal generating apparatus is provided for readily generating multiple phase signals. The multi-phase signal generating apparatus comprises a signal data storage which stores a plurality of data segments for determining a predetermined period of one signal. A data segment selector circuit selects segments for constituting the phase signals from a plurality of data segments stored in the signal data storage for determining the predetermined period of a signal in each of a plurality of segment intervals which make up a phase signal cycle for generating a phase signal. Each phase signal generator circuit forms each phase signal using a plurality of selected segments for each phase signal during a plurality of segment intervals.

Abstract: A display control circuit is provided for displaying a modulated image such as a persistence image. An image display may includes the display control circuit. The control circuit adds persistence pixel data for persistence display to input pixel data within an input image frame to generate display pixel data within a display image frame which is supplied to a display. The control circuit includes a persistence pixel data generator and a persistence pixel data adder.

Abstract: The present invention relates to a device (10) for converting an AC voltage from the mains electricity supply into a DC voltage of predetermined level (and waveform), comprising:—a rectifier circuit (16, 17, 18, 19) for connecting to the mains electricity supply;—a switching circuit connected to the rectifier circuit;—a main transformer (26) connected to the switching circuit and—an auxiliary transformer (28) which is connected to the switching circuit and the secondary winding of which is coupled to the secondary winding of the main transformer such that the current through the switching circuit and the main transformer is limited to a predetermined value.

Abstract: An adjustable right angle electrical plug with an interchangeable plug assembly has a casing, an interchangeable plug assembly and an electric cord. The casing is hollow and has a base, a cover and two resilient contacts. The cover is mounted on the base and has a plug recess. The plug recess is symmetric. The resilient contacts protrude into the plug recess. The interchangeable plug assembly is mounted detachably in the plug recess has a body, two prongs and a bottom cover. The body is hollow, corresponds to the plug recess and has an open bottom. The prongs are mounted through and protrude from the body and may be flat blades or cylindrical prongs. The bottom cover has two curved contacts. Each curved contact extends through the bottom cover at two places separated by 90°, makes contact with one of the resilient contacts and is connected to one of the prongs.

Abstract: A plasma display panel is provided. The plasma display panel includes a front glass substrate, a transparent electrode formed on the front glass substrate, a black layer formed on an upper part of the transparent electrode, and a bus electrode formed on an upper part of the black layer. The width of the bus electrode is less than the width of the black layer.

Abstract: A green sheet, a plasma display panel using the green sheet and a method of manufacturing a plasma display panel are provided. The method of manufacturing the plasma display panel comprises laminating a green sheet comprising a dielectric layer and an electrode pattern on a substrate, and firing the substrate. The plasma display panel comprises a substrate, a black layer formed on the substrate, an electrode formed on the black layer, and a dielectric layer formed on the electrode, the black layer and an upper surface of the substrate. Further, there is a difference in elevation among the dielectric layer on the electrode, the dielectric layer on the black layer and the dielectric layer on the upper surface of the substrate. The green sheet comprises a dielectric layer, and a conductive layer formed on the dielectric layer.

Abstract: A waveform monitor comprises: means (51) for converting a compressed video signal into uncompressed parallel data; means (33) for converting the parallel data into waveform display data; means (52) for analyzing a transmission status of the compressed video signal and generating analysis data; and means (36) for displaying the waveform display data and the analysis data simultaneously. The waveform monitor can further comprise: means (31) for converting an SDI signal into parallel data; and means (32) for analyzing a transmission status of the SDI signal and generating the analysis data.

Abstract: A genlock device comprises: means (31) for inputting an external reference signal; means (32,33,34,36,39,40,41,42,44) for generating a master reference clock signal synchronized in phase with the external reference signal; and means (37) for storing a genlock state. The genlock state includes, for example, absence of a synchronization signal in the external reference signal. The genlock device can further comprise: means (45) for storing a voltage value determined so that a voltage controlled oscillator (40) oscillates a signal having a frequency higher or lower by a predetermined value than a reference frequency of the voltage controlled oscillator; and means (44) for judging whether a voltage value which controls the voltage controlled oscillator is larger or smaller than the voltage value.

Abstract: A bit error rate (BER) measuring apparatus is provided for measuring BER of an out-of-band tuner. The BER measuring apparatus generates a test signal for measuring the BER of the out-of-band tuner using a transport stream including a pseudo-random bit string (PRBS). In one embodiment, the BER measuring apparatus comprises a BER test signal generator that generates the test signal which includes a transport stream for transmission. The BER measuring apparatus also comprises a BER detector that detects the BER from a received test signal generated by the tuner in response to the test signal from the BER test signal generator. In one embodiment, the test signal generator comprises a PRBS generator that generates a first PRBS, and a transport stream framing circuit that frames the first PRBS into a transport stream form to generate the transport stream for transmission.

Abstract: An apparatus comprises input means, detection means and a selector, and automatically detects a kind of serial signal used in BER measurement. The input means receives at least two signals which include a data signal, and a clock signal having a period corresponding to one bit of the data signal. The detection means determines which one of the at least two signals is a clock signal or a data signal. The selector outputs the signal determined to be a clock signal from a clock signal terminal and outputs the signal determined to be a data signal from a data signal terminal.