Abstract: A semiconductor device isolation method includes sequentially forming a first insulating film and a second insulating film on a semiconductor substrate, exposing a predetermined portion of the surface of the semiconductor substrate, forming a third insulating on the exposed surface of the semiconductor substrate and the second insulating film, forming sidewall spacers composed of the third insulating film at the sidewall surfaces of the first and second insulating films, forming a trench by performing an etching by a predetermined depth using the sidewall spacers as a mask, removing the sidewall spacers, filling a high density plasma chemical vapor deposition (HDP CVD) oxide in the trench, and removing the first and second insulating films.

Abstract: A CMOS device includes a first conductivity type semiconductor substrate having an active region, the active region including two second conductivity type of impurity regions and a first channel region between the two second conductivity type impurity regions, a field insulation region on the semiconductor substrate for electrical isolation of the active region from other adjacent active regions, a second conductivity type semiconductor layer on the field insulation layer, the semiconductor layer including two first conductivity type impurity regions and a second channel region between the two first conductivity type impurity regions, and a gate electrode over the first channel region in the active region and the second channel region in the semiconductor layer.

Abstract: Disclosed are an address detecting device of an ethernet controller and an address detecting method thereof which improve processing ability of a packet by prompt comparison between a destination address and a group address.

Abstract: An LCD panel driving circuit, includes a timing control circuit determining an output timing of a digital video signal and vertical/horizontal synchronizing signals and outputting the digital video signal and a row line driving signal, a D/A converter circuit coupled to the timing control circuit and receiving the digital video signal from the timing control circuit and outputting analog video signals to be sequentially applied to groups of column driver lines, a gamma correction circuit coupled to the D/A converter circuit and applying a correction signal to the D/A converter circuit, a sequence control circuit receiving the horizontal synchronizing signal and sequentially outputting a column driver enable signal, a column driver coupled to the sequence control circuit and the D/A converter circuit for sequentially receiving the analog video signals from the D/A converter circuit and subsequently outputting the analog video signals to different groups of column driver lines cell of a LCD panel, and a row dri

Abstract: A high-speed flip-flop is provided that implements a low power consumption and a high-speed response caused by an interior capacitance reduction. A D flip-flop includes a first latch that receives a clock signal and a data signal to produce a first output signal. A second latch receives the first output signal and the clock signal to produce a second output signal. A third latch receives the second output signal and the clock signal to produce a third output signal. An inverter receives the third output signal to produce the data signal on a rising or falling edge of the clock signal. The first and second latches are preferably ratioed latches having series coupled pull-up and pull-down elements. The third latch is preferably a clock operated latch.

Abstract: A method for fabricating a bipolar transistor improves the fast characteristics of the transistor at low operating voltages. An oxide film is formed on a semiconductor substrate, in which a buried layer is formed, and a floating poly base is formed on the oxide film. An insulating film is then formed on the entire surface of the semiconductor substrate including the floating poly base. The insulating film and the floating poly base are etched to define a base region and a collector region, and a first epitaxial layer is formed in the base and collector regions, with the first epitaxial layer having a smaller thickness than the oxide film. A second epitaxial layer is formed on the first epitaxial layer, and impurities are implanted into the second epitaxial layer in the base and collector regions. A second polysilicon layer is then formed on the second epitaxial layer in the base region, and electrodes are formed on the semiconductor surface.

Abstract: Device for delaying a clock signal using a ring delay is disclosed. The device can include a delay for delaying an external clock signal eCLK as much as time delays d1+d2 of a time delay d1 occurring on reception and a time delay d2 occurring on driving an output buffer, a pulse generator for receiving the clock signal from the delay and generating rectangular pulses synchronous to rising edges, and a ring delay having a plurality of unit delays connected in a ring form for delaying and circulating the pulse signal generated in the pulse generator as well as latching a signal from each unit delay synchronous to the clock signal rCLK received in the chip. The first clock signal delay is for delaying the clock signal rCLK in a course corresponding to a number of circulation, and a second clock signal delay is for making a fine delay of the clock signal from the first clock signal delay in response to a latch signal from the ring delay.

Abstract: A flash memory cell and a method of fabricating the same are disclosed in the present invention. A method of fabricating a flash memory cell having a substrate includes the steps of forming a buried data line in the substrate, forming an insulating layer on the substrate including the buried data line, forming an erase gate on the insulating layer, forming an isolation layer by etching the insulating layer with the erase gate as a mask, forming a floating gate having an indentation at least, the indentation of the floating gate corresponding to the erase gate, and forming a control gate on the floating gate.A flash memory cell includes a substrate, first and second buried data lines in the substrate, an isolation layer on the substrate, a floating gate including a indentation at least on the substrate between the first and second buried data lines, an erase gate over the isolation layer, a part of the erase gate being inserted into the indentation, and a control gates on the floating gate.

Abstract: A delay circuit which is capable of maintaining a constant delay time. The circuit includes a plurality of first delay circuits connected in series and each having an inverter for inverting an input voltage signal, and a variable capacitor connected to an output terminal of the inverter.

Abstract: A semiconductor device and a method for manufacturing the same that forms a self-aligned contact hole between two gate lines. A substrate is provided that has a first gate line formed thereon. An insulator is formed on the first gate line and substrate. Then a portion of the insulator and a portion of the first gate line is selectively removed to split the first gate line into a second gate line and a third gate line and to concurrently expose the substrate. Thus, producing a self-aligned contact hole between the second and third gate lines.

Abstract: Semiconductor device and method for fabricating the same, is disclosed, in which a gate insulating film is formed thicker at portions opposite to edge portions of a gate electrode for preventing the hot carrier possible to occur due to a strong electric field of the gate electrode, that can improve a device reliability, the device including a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, the gate insulating film having both end portions formed thicker than a center portion, a gate electrode formed on the gate insulating film, the gate electrode having a center portion formed thicker than portions thereof on both sides of the gate insulating film, and impurity regions formed in surfaces of the semiconductor substrate on both sides of the gate electrode, and the method including the steps of (1) forming a gate insulating film on a semiconductor substrate, and forming a gate electrode having a thicker center portion on the gate insulating film, (2) expanding thicknesses o

Abstract: A metal wiring for semiconductor devices having a double-layer passivation film structure consisting of an intermetallic compound layer formed on a copper thin film and made of a metal reacting with copper to form an intermetallic compound and a metal nitride layer formed over the intermetallic compound. This double-layer passivation film structure is obtained by depositing a metal layer, capable of reacting with copper to form an intermetallic compound, over the copper wiring, and annealing the metal layer in a nitrogen atmosphere, thereby forming an intermetallic compound layer over the copper wiring. By virtue of the double-layer passivation film structure, the copper wiring has a great improvement in the reliability. A metal silicide layer is formed between a diffusion region and a diffusion barrier layer in the contact hole of the semiconductor device. The diffusion barrier layer, which is formed on an insulating layer doped with nitrogen ions, is changed into a metal nitride film.

Abstract: A reticle cleaning apparatus for a wafer exposure system includes a chamber enclosing the reticle, a door opening and closing at least one side of the chamber, a door switching member opening and closing the door coupled to the chamber including the door, a gas injection nozzle at an upper portion of the chamber, a nozzle transport member moving the gas injection nozzle in a vertical direction, a gas supply member supplying a cleaning gas into the gas injection nozzle, an ion injection nozzle over the gas injection nozzle, an ion supply member supplying ions into the ion injection nozzle, and a drain member draining the cleaning gas outside the chamber.

Abstract: The present invention relates to a method of forming an interconnection for a semiconductor device using copper. The method of the invention, including the steps of forming an insulating layer having a groove on a semiconductor substrate containing active elements; forming and depositing a copper thin film on the insulating layer including the groove; and reflowing the copper thin film, may reflow the copper thin film deposited on the semiconductor substrate having a high-step surface for less than 30 min. below 450.degree. C., which show improved annealing conditions as compared with the conventional art. In addition, by reducing consumption of thermal energy in accordance with a low-temperature process, copper is restrained from being rapidly diffused through a silicon substrate, electrodes, etc. when forming the interconnection for the semiconductor device, thus improving productivity of the semiconductor devices.

Abstract: An address transition detection summation circuit is provided that selectively maintains an input voltage of a pull-up circuit at an intermediate level during a pull-up time. The address transition detection summation circuit includes a pull-up circuit and an address transition detection summation unit for summing a plurality of ATD signals. A delay unit delays an address transition detection summation node signal and can determine a pulse width of the address transition detection summation signal. An input signal generation unit can maintain the input level of the pull-up circuit at an intermediate level. Thus, although a short pulse ATD signal or a standard pulse ATD signal is inputted, a width of an address transition detection summation signal is made as wide as the ATD signal. Thus, the address transition detection summation signal more rapidly responds to the short pulse, which can prevent a failure of a chip operation.

Abstract: The DRAM cell includes a first transistor, a second transistor, and a capacitor. The first and second transistors each have a gate, a source, and a drain electrode. The gate electrode of the second transistor is connected to one of the source and drain electrodes of the first transistor, and a first electrode of the capacitor is connected to the gate electrode of the second transistor. Also, a second electrode of the capacitor is connected to one of the source and drain electrodes of the second transistor. One of the source and drain electrodes of the second transistor not connected to the second electrode of the capacitor is connected to the gate electrode of the second transistor. Accordingly, the second transistor is on when a logic value of "1" is stored in the gate thereof, and off when a logic value of `0` is stored in the gate thereof.

Abstract: A charge-coupled device includes a first P-type well formed in an N-type semiconductor substrate, a second P-type well formed repeatedly the first P-type well region, a charge-transfer region (BCCD) formed within the second P-type well region, an N-type photodiode region (PDN) formed in the upper portion of the first P-type well so as to be isolated from the charge-transfer region, a first high concentration P-type photodiode region (first PDP.sup.+ region) formed in the upper surface of the N-type photodiode region excluding the charge-transfer region and serving as a charge-isolating layer, first and second poly-gates formed repeatedly on the charge-transfer region, and a second high concentration self aligned P-type photodiode region (second PDP.sup.+ region) formed in the surface of the first high concentration P-type photodiode region. The charge-isolating region is thin to extend the potential pocket of each light-conversion PDN region.

Abstract: A nonvolatile memory has a cell structure of one transistor/one capacitor/one resistor (1T/1C/1R). Such a structure allows high speed access operation and efficiently prevent a reference cell from being degraded. The nonvolatile memory includes a first memory cell array having a plurality of first word lines formed in a first direction, a plurality of bit lines in a second direction, a first common signal line formed in one of first and second directions, and a plurality of first memory cells. Each first memory cell is coupled to a corresponding first word line, a corresponding bit line, and the first common signal line. A controller is coupled to the plurality of bit lines, and the controller allows at least one of reading of data stored in a corresponding first memory cell and writing of data to a corresponding first memory cell.

Abstract: A control apparatus and method is provided for controlling operations of functional units in systems. The control apparatus and method implement a set of operations that can include dependencies between the functional units of a system to complete each operation. For example, in an asynchronous digital processor, self-timing and inter-block communication are used to implement a self-timed scheduler. The self-timed scheduler and method implement an instruction set using a plurality of functional units of the asynchronous digital processor. A scheduler can include a scheduler decoder that decodes each instruction to generate functional unit schedule and control information, a communication device and a plurality of scheduler functional unit controllers, wherein each of the scheduler functional unit controllers corresponds to one of the plurality of functional units of a system.

Abstract: A power consumption control apparatus and method for an asynchronous system is provided that reduces power consumption by selecting one of a plurality of power consumption levels for the system. The power consumption levels can be determined based on work load requirements of the system and can be implemented for the system or portions thereof using a single block of the system. The asynchronous system includes a plurality of intercoupled functional units and a power control circuit coupled to a selected one of the plurality of functional units to determine at least one of a first and a second operating speed of a selected functional unit.