Abstract: A digital audio processor includes an input unit for converting an externally applied signal to a digital audio processor preferred type and a gain controller for multiplying a data converted in the input unit to control an input data size. A signal processor processes a signal outputted from the gain controller and a volume controller multiplies an output signal of the signal processor to control an output volume size. A first comparator compares a present signal and a previous signal respectively output from the input unit and a second comparator compares a present signal and a previous signal respectively output from the gain controller. A noise gate decreases a volume to a certain level when a present data is smaller than a previous data based on output values of the first and second comparators. An output unit converts an output value of the noise gate to an external output data type. The apparatus eliminates noise occurrence when a data size for an internal process becomes too small.

Abstract: Methods for fabricating a semiconductor device suitable for increasing process tolerance of the device are disclosed. One method includes the steps of sequentially forming an insulating layer, a planarization layer, and a nitride layer over cell transistors formed on a substrate; patterning the nitride layer to define first contact holes; forming polysilicon sidewall spacers on the sides of the patterned nitride layer; removing portions of the planarization layer and the insulating layer using the patterned nitride layer and the polysilicon sidewall spacers, so as to define second contact holes; and forming pad polysilicon layers in the second contact holes, so as to expose portions of the patterned nitride layer.

Abstract: A charge coupled device and a method of manufacturing a charged coupled device includes a semiconductor substrate, a plurality of photoelectrical conversion cells formed in the semiconductor substrate in a matrix form, a plurality of vertical charge coupled device regions formed between the plurality of photoelectrical conversion cells, a plurality of stripe layers formed on the semiconductor substrate and corresponding to the plurality of vertical charge coupled device regions, and a plurality of microlenses formed on the semiconductor substrate and corresponding to the plurality of photoelectrical conversion cells.

Abstract: A lead frame and a semiconductor chip package includes supporters on a lead frame paddle and tiebars using the same for preventing undesired paddle bending which may occur due to the pressure of an epoxy molding compound during the molding process. The supports also allow improved heat dissipation during the molding process of the semiconductor chip package and mounting process of the package onto a printed circuit board.

Abstract: An analog-to-digital converter includes a sample and hold circuit for sampling and holding an input analog signal and outputting an analog voltage, a selection code generator for generating a selection code corresponding to an operation mode for a number of conversion bits and a number of samples, a decoder for generating an enable signal corresponding to the selection code, a comparator for comparing an external voltage with the analog voltage and outputting a digital value, a conversion data register for storing the digital value and outputting a final digital value, a digital-to-analog converter for outputting the external voltage by inputting the digital value and a reference voltage stored in the ADR, a multiplexer for selecting a signal path for the operation mode selected by the selection code generator, a shift register for determining a number of registers for the operation mode selected by the selection code generator, a counter for counting a number of shifts of the shift register and determining t

Abstract: A memory device and a method of manufacturing the same in accordance with the present invention has an improved writing and erasing efficiency and an improved reliability. The memory device includes a first conductivity type substrate having second conductivity type source and drain regions spaced apart from each other. A source electrode having a T-shaped rail structure is formed in contact with the source region, and a drain electrode having a T-shaped rail structure is formed in contact with the drain region. An I-shaped floating gate is formed on the substrate between the source electrode and the drain electrode with a control gate formed on the floating gate.

Abstract: A lead frame structure and semiconductor package using the same and fabrication method thereof is provided that decreases noise by providing prescribed impedances for leads of a lead frame. The lead frame structure for the semiconductor package includes a paddle, a plurality of leads regularly aligned outside the paddle, and upper and lower dielectric adhesive layers sandwiching the plurality of leads. Upper and lower dielectric layers are attached on an upper surface of the upper dielectric adhesive layer and a lower surface of the lower dielectric adhesive layer. Upper and lower metallic polar plates formed on an upper surface of the upper dielectric layer and a lower surface of the lower dielectric layer.

Abstract: A Metal Oxide Silicon Field Effect Transistor (MOSFET) and method includes a gate electrode pattern formed over a gate insulation layer on a semiconductor substrate. A pair of first impurity regions are respectively formed in an upper side surface of the substrate and adjacent to a side of the gate electrode pattern. A pair of first side wall spacers are respectively formed adjacent to a side wall of the gate electrode pattern, and a pair of air gaps are respectively formed between the gate electrode pattern and each of the side wall spacers. The MOSFET and method solve an increase problem of a fringing capacitor between a source and a gate electrode by forming an air gap along a side of the gate electrode. Further, a semiconductor chip area becomes decreased by forming a source and drain in a vertical structure. The source and drain formed of a side wall spacer further prevents a short channel effect from occurring. In addition, a cost reduction is achieved by adopting a self-alignment process.

Abstract: A CCD image device in which the potential variation of a charge transferring region caused by a CST layer is minimized to enhance the charge transfer efficiency, is disclosed including a plurality of photo-detectors arranged regularly in row and column directions in the surface of a substrate of a first conductivity type; a plurality of charge transferring regions of a second conductivity type formed between the photo-detectors of the row direction; and a channel stop layer formed in the surface of the substrate in order to electrically insulate the respective photo-detectors and the respective charge transferring regions from each other. A CST doping concentration reducing region for decreasing the doping concentration of the channel stop layer is formed at least one in each part to which the neighboring two photo-detectors are adjacent.

Abstract: A split wordline ferroelectric memory does not utilize plate lines and a circuit for driving the same is disclosed. The memory including unit cell arrays and each array has a plurality of split wordlines (SWLs) arranged in a first direction at fixed intervals, and a plurality of bitlines arranged in a second direction vertical to each of the SWLs at fixed intervals. A ferroelectric unit memory cell is arranged in each pair of adjacent two SWLs and adjacent two bitlines.

Abstract: A fabrication method for a semiconductor memory device includes the steps of forming a gate pattern on a semiconductor substrate; forming first and second sidewall spacers at sides of the gate pattern; performing an ion=implantation of a high concentration impurity using the gate pattern and the first and second sidewall spacers as a mask, thereby forming an impurity diffusion region in the semiconductor substrate; performing an ion-implantation of a transition metal on the semiconductor substrate including the gate pattern and the first and second sidewall spacers, and then forming a polysilicide and a silicide by annealing; and removing the second sidewall spacers.

Abstract: A dry etching method for a multilayer film is disclosed, which is capable of dry-etching a multilayer film such as a titanium polyside (a polysilicon layer and a titanium silicide layer) and includes the steps of a first step for anisotropically etching the titanium silicide layer using a plasma containing Cl.sub.2 /N.sub.2 gas, and a second step for anisotropically etching the polysilicon layer using a plasma containing Cl.sub.2 /O.sub.2.

Abstract: Disclosed are an isolation film of a semiconductor device and a method for fabricating the same, which prevent the isolation film from being damaged due to misalignment when forming a contact hole in a region adjacent to the isolation film, to ensure stable effective isolation distance. The isolation film of a semiconductor device includes a semiconductor substrate, a lower isolation film formed in the semiconductor substrate, and an upper isolation film formed on the lower isolation film, with a material having etching selectivity different from the lower isolation film.

Abstract: A redundancy circuit for a semiconductor integrated circuit is disclosed, which includes each cell of the column redundancy cell block corresponding to each cell of the cell sub-array is connected opposite to the connection of the cells of the cell sub-array, wherein a state that an electric charge corresponding to a data written into each cell of the cell sub-array and the column redundancy cell block is discharged, is measured for thus accurately checking the position of the repaired cell after the redundancy operation is performed.

Abstract: An improved lead frame with a pre-mold paddle for a semiconductor chip package which prevents delamination and cracking between a mold body and the pre-mold paddle on which a semiconductor chip in the semiconductor chip package is placed.

Abstract: Capacitor in a semiconductor device suitable for diffusion prevention between a lower electrode and a polysilicon and oxidation prevention of a barrier metal layer and a method for manufacturing the same are disclosed. The capacitor in a semiconductor device includes a semiconductor substrate, an insulating layer having a contact hole on the substrate, a plug formed in the contact hole, a first barrier layer on the plug, a second barrier layer on the first barrier layer, a lower electrode on the second barrier layer, a dielectric layer on the lower electrode, and an upper electrode on the dielectric layer.

Abstract: Disclosed is a transistor structure having a semiconductor substrate with a active region and a field region, a recess region being defined by either the field region or the active region, a gate electrode formed on portions of the active and recess region, and impurity regions formed in the active region of the semiconductor substrate on either side of the gate electrode. The transistor structure has an active region with at least one groove formed therein, and the transistor structure being formed for a low voltage operation.

Abstract: The ferroelectric memory device of the present invention controls the data input and output timing in the memory by a combination of the changes of X, Y, Z addresses and chip enable signals so that the ferroelectric memory device is enabled. The ferroelectric memory device includes a plurality of bitlines and a plurality of bitbarlines intersect a plurality of split wordlines, which comprises of a pair of a first split wordline and a second split wordline. A plurality of memory cells are formed between the first and second split wordlines, and a timing controller controls the data input and output timing of the memory cells according to the changes of the X, Y, Z addresses and the chip enable signals.

Abstract: A high voltage generating circuit is disclosed, which reduces power consumption due to unnecessary operations. The high voltage generating circuit includes a charge pump for pumping an output voltage in response to a first pump control signal and a second pump control signal which are synchronizing signals, a first level detector operated by an externally applied enable signal and for detecting a first level from the output voltage and outputting a first level signal, a first pump controller for generating a control signal using the first level signal and a reference signal, and outputting the first pump control signal using the control signal and an externally applied inverted clock signal, a second level detector operated by the control signal and for detecting a second level from the output voltage and outputting a second level signal, and a second pump controller for outputting the second pump control signal using the second level signal, the reference signal and an externally applied clock signal.

Abstract: An SOI semiconductor substrate and a fabrication method therefor which are capable of preventing a depletion region due to a fixed electric charge occurring at a junction surface from being formed in a silicon wafer within which an integrated circuit is to be formed. The SOI semiconductor substrate includes a first silicon wafer, a first oxide layer formed on an upper surface of the first silicon wafer, an undoped polysilicon layer formed on an upper surface of the first oxide layer, and a second silicon wafer formed on an upper surface of the polysilicon layer.