Abstract: Hybrid analog-digital processing systems are described. An example of a hybrid analog-digital processing system includes photonic accelerator configured to perform matrix-vector multiplication using light. The photonic accelerator exhibits a frequency response having a first bandwidth (e.g., less than 3 GHz). The hybrid analog-digital processing system further includes a plurality of analog-to-digital converters (ADCs) coupled to the photonic accelerator, and a plurality of digital equalizers coupled to the plurality of ADCs, wherein the digital equalizers are configured to set a frequency response of the hybrid analog-digital processing system to a second bandwidth greater than the first bandwidth.

Abstract: Described herein are electronic-photonic packages including photonic integrated circuits (PIC) that are assembled using hybrid bonding techniques and that communicate with external electronic dies using through silicon vias (TSVs). PICs of the types described herein may be used to support optical-domain communication between electronic devices, whether in the form of inter-chip communication or intra-chip communication. A package may include a PIC comprising a photonic layer comprising a plurality of controllable photonic devices and a first plurality of TSVs, and an electronic layer hybrid-bonded to the photonic layer, the electronic layer comprising a second plurality of TSVs coupled to the first plurality of TSVs, and electronic circuitry configured to control the controllable photonic devices. The package may further include a first electronic die mounted on the PIC and coupled to the first plurality of TSVs or the second plurality of TSVs.

Abstract: Described herein are wavelength division multiplexing (WDM) transceivers configured to support fast, bidirectional communication over optical channels. An optical transceiver comprises a transmitter, a receiver, an input/output (I/O) port and an optical interleaver. The transmitter comprises a first bus waveguide and a plurality of optical modulators coupled to the first bus waveguide, each of the optical modulators being resonant at a respective wavelengths in a first wavelength set. The receiver comprises a second bus waveguide and a plurality of optical filters coupled to the second bus waveguide, each of the optical filters being resonant at a respective wavelength in a second wavelength set. The (I/O) port is coupled to an optical channel.

Abstract: Described herein are photonic communication platforms that can overcome the memory bottleneck problem, thereby enabling scaling of memory capacity and bandwidth well beyond what is possible with conventional computing systems. Some embodiments provide photonic communication platforms that involve use of photonic modules. Each photonic module includes programmable photonic circuits for placing the module in optical communication with other modules based on the needs of a particular application. The architecture developed by the inventors relies on the use of common photomask sets (or at least one common photomask) to fabricate multiple photonic modules in a single wafer. Photonic modules in multiple wafers can be linked together into a communication platform using optical or electronic means.

Abstract: Described herein are architectures configured to enable wavelength remapping in on-chip wavelength division multiplexing (WDM) optical systems. An optical switching network receives light having wavelengths corresponding to wavelength set A at a first subset of the plurality of inputs and light having wavelengths corresponding to wavelength set B at a second subset of the plurality of inputs. The wavelengths are received in accordance with a first spatial order. In response, the optical switching network may change the order from the first spatial order to a second spatial order. For example, the optical switching network may output light having wavelengths corresponding to wavelength set A at a first subset of the plurality of outputs and light having wavelengths corresponding to wavelength set B at a second subset of the plurality of outputs in accordance with the second spatial order.

Abstract: Photonic interposers that enable low-power, high-bandwidth inter-chip (e.g., board-level and/or rack-level) as well as intra-chip communication are described. Described herein are techniques, architectures and processes that improve upon the performance of conventional computers. Some embodiments provide photonic interposers that use photonic tiles, where each tile includes programmable photonic circuits that can be programmed based on the needs of a particular computer architecture. Some tiles are instantiations of a common template tile that are stitched together in a 1D or a 2D arrangement. Some embodiments described herein provide a programmable physical network designed to connect pairs of tiles together with photonic links.

Abstract: Hybrid analog-digital processing systems are described. An example of a hybrid analog-digital processing system includes photonic accelerator configured to perform matrix-vector multiplication using light. The photonic accelerator exhibits a frequency response having a first bandwidth (e.g., less than 3 GHz). The hybrid analog-digital processing system further includes a plurality of analog-to-digital converters (ADCs) coupled to the photonic accelerator, and a plurality of digital equalizers coupled to the plurality of ADCs, wherein the digital equalizers are configured to set a frequency response of the hybrid analog-digital processing system to a second bandwidth greater than the first bandwidth.

Abstract: Described herein are wavelength division multiplexing (WDM) transceivers configured to support fast, bidirectional communication over optical channels. An optical transceiver comprises a transmitter, a receiver, an input/output (I/O) port and an optical interleaver. The transmitter comprises a first bus waveguide and a plurality of optical modulators coupled to the first bus waveguide, each of the optical modulators being resonant at a respective wavelengths in a first wavelength set. The receiver comprises a second bus waveguide and a plurality of optical filters coupled to the second bus waveguide, each of the optical filters being resonant at a respective wavelength in a second wavelength set. The (I/O) port is coupled to an optical channel.

Abstract: Systems and methods for performing signed matrix operations using a linear photonic processor are provided. The linear photonic processor is formed as an array of first amplitude modulators and second amplitude modulators, the first amplitude modulators configured to encode elements of a vector into first optical signals and the second amplitude modulators configured to encode a product between the vector elements and matrix elements into second optical signals. An apparatus may be used to implement a signed value of an output of the linear processor. The linear photonic processor may be configured to perform matrix-vector and/or matrix-matrix operations.

Abstract: Described herein are packages in which photonic chiplets are disposed in recesses defined on an underlying substrate. Positioning chiplets in this way allows short trace lengths between the electrical chips and the optical converters, V-groove fiber assemblies that can be attached along any direction of a photonic chiplet (north-south and/or west-east) and easy access to the electrical chips for power and signals. A package may include a substrate having a recess defined near an edge of the substrate, a photonic chiplet disposed in the recess, an electrical chiplet disposed at least in part on the photonic chiplet, and a fiber optically coupled to the photonic chiplet at the edge of the substrate. The electrical chiplet may be disposed in part on the photonic chiplet and in part on the top surface of the substrate.

Abstract: Described herein are compact, power efficient photonic processors deigned to handle general matrix-matrix (GEMM) operations. A photonic processor may comprise a controller, an optical interferometer, a plurality of signal drivers, and an optical receiver. The controller is configured to obtain a vector of input values and a matrix of parameters. The optical interferometer comprises an output and a plurality of optical phase shifters. Each signal driver of the plurality of signal drivers is configured to control a respective phase shifter to phase shift light traveling in the optical interferometer based on i) a polarity set by a respective parameter of the matrix, and ii) an amount set by a respective input value of the vector. The optical receiver is coupled to the output of the optical interferometer.

Abstract: Aspects of the present application relate to an optical phase shifter including a first waveguide defined in a first semiconductor layer, the first waveguide comprising a single-mode portion, a multi-mode portion, and a tapered portion coupling the single-mode portion to the multi-mode portion. A second waveguide is defined in a second semiconductor layer, the second waveguide having a tapered portion and a tip, wherein the tapered portion of the second waveguide overlaps with the tapered portion of the first waveguide. For tuning the phase change, a first electrically resistive path, defined at least partially in the first semiconductor layer, is included. The first electrically resistive path intersects the multi-mode portion of the first waveguide.

Abstract: Systems and methods for performing matrix operations using a photonic processor are provided. The photonic processor includes encoders configured to encode a numerical value into an optical signal and optical multiplication devices configured to output an electrical signal proportional to a product of one or more encoded values. The optical multiplication devices include a first input waveguide, a second input waveguide, a coupler circuit coupled to the first input waveguide and the second input waveguide, a first detector and a second detector coupled to the coupler circuit, and a circuit coupled to the first detector and second detector and configured to output a current that is proportional to a product of a first input value and a second input value.

Abstract: Photonic interposers that enable low-power, high-bandwidth inter-chip (e.g., board-level and/or rack-level) as well as intra-chip communication are described. Described herein are techniques, architectures and processes that improve upon the performance of conventional computers. Some embodiments provide photonic interposers that use photonic tiles, where each tile includes programmable photonic circuits that can be programmed based on the needs of a particular computer architecture. Some tiles are instantiations of a common template tile that are stitched together in a 1D or a 2D arrangement. Some embodiments described herein provide a programmable physical network designed to connect pairs of tiles together with photonic links.

Abstract: Described herein are photonic communication platforms that permit use by multiple users in a secure way. A platform comprises a substrate, a first photonic circuit monolithically integrated with the substrate, and a second photonic circuit monolithically integrated with the substrate. The first photonic circuit is patterned with a first plurality of photonic modules, the photonic modules of the first plurality being copies of a common template photonic module The second photonic circuit is patterned with a second plurality of photonic modules, the photonic modules of the second plurality being copies of the common template photonic module. A photonic link couples the first photonic circuit to the second photonic circuit. A controller optically isolates the first photonic circuit from the second photonic circuit by optically interrupting the photonic link.

Abstract: Aspects relate to a photonic processing system, a photonic processor, and a method of performing matrix-vector multiplication. An optical encoder may encode an input vector into a first plurality of optical signals. A photonic processor may receive the first plurality of optical signals; perform a plurality of operations on the first plurality of optical signals, the plurality of operations implementing a matrix multiplication of the input vector by a matrix; and output a second plurality of optical signals representing an output vector. An optical receiver may detect the second plurality of optical signals and output an electrical digital representation of the output vector.

Abstract: Described herein are balanced, bidirectional, optical communication networks. These networks may be used in large-scale settings, including in networks including more than one hundred nodes or more than one thousands nodes. A network may include a plurality of nodes. Each node comprises a plurality of optical transceivers of a first type and a plurality of optical transceivers of a second type. The types differ from each other in a characteristic of light transmitted by the respective optical transceiver. The optical transceivers of the first type are in equal numbers across the plurality of nodes and the optical transceivers of the second type are also in equal numbers across the plurality of nodes. A plurality of optical channels connect the nodes with one another by coupling optical transceivers of the first type with optical transceivers of the second type. The optical channel support bidirectional communication between the connected nodes.

Abstract: Described herein are embodiments of a photonic computing system comprising one or more processors in communication with disaggregated memory through one or more optical channels. The disaggregated memory comprises multiple memory units placed on a photonic substrate that includes a photonic network that can be programmed to configure which of the memory units can be accessed by each of the processor(s). The disaggregated memory includes a memory controller for reading and writing data to/from the memory units. The memory controller may be configured to perform processing in concert with the processor(s).

Abstract: Described herein is a packaging approach that employs a remapping layer to maintain compatibility to different types of electronic chips while allowing chip designers to standardize the layout of the electrical interface of a photonic interposer. A remapping layer remaps the electrical interface of an electronic chip to the electrical interface of a photonic interposer. Remapping layers may be implemented in various ways, including for example as monolithic electronic interposers and/or as individual remapping chips. In some embodiments, to reduce manufacturing costs, remapping layers may be implemented using passive electronics (without transistors). Because remapping layers are significantly less costly to manufacture than photonic interposers, shifting the need to provide ad hoc electrical interfaces from the photonic interposer to the remapping layer enhances the applicability of photonic interposers in computational, telecom and datacom settings.

Abstract: Photonic interconnect systems are described. A fiber connects a first photonic integrated circuit (PIC) to a second PIC. The fiber is non-polarization maintaining and as a results creates polarization drift. As a result, the polarization appearing at the output of a fiber may be different from the polarization launched at the input of the fiber. To reduce the negative effects of polarization drift, each PIC may be equipped with a polarization locker. Control circuitry is configured to control the first and second polarization lockers by setting one of the first and second polarization lockers to an active configuration and setting the other of the first and second polarization lockers to a passive configuration. Controlling the polarization lockers in this way prevents inconsistencies in polarization without having to expend additional resources that would otherwise be required to communicate the phase shift across the fiber.