Abstract: Described herein are techniques of training a machine learning model and performing inference using an analog processor. Some embodiments mitigate the loss in performance of a machine learning model resulting from a lower precision of an analog processor by using an adaptive block floating-point representation of numbers for the analog processor. Some embodiments mitigate the loss in performance of a machine learning model due to noise that is present when using an analog processor. The techniques involve training the machine learning model such that it is robust to noise.

Abstract: Aspects of the present disclosure provide an aligned storage strategy for stripes within a long vector for a vector processor, such that the extra computation needed to track strides between input stripes and output stripes may be eliminated. As a result, the stripe locations are located in a more predictable memory access pattern such that memory access bandwidth may be improved and the tendency for memory error may be reduced.

Abstract: Parallelization and pipelining techniques that can be applied to multi-core analog accelerators are described. The techniques descried herein improve performance of matrix multiplication (e.g., tensor-tensor multiplication, matrix-matrix multiplication or matrix-vector multiplication). The parallelization and pipelining techniques developed by the inventors and described herein focus on maintaining a high utilization of the processing cores. A representative processing systemin includes an analog accelerator, a digital processor, and a controller. The controller is configured to control the analog accelerator to output data using linear operations and to control the digital processor to perform non-linear operations based on the output data.

Abstract: Aspects of the present disclosure are directed to an efficient data transfer strategy in which data transfer is scheduled based on a prediction of the internal memory utilization due to computational workload throughout its runtime. According to one aspect, the DMA transfer may be performed opportunistically: whenever internal buffer memory is available and the additional internal memory usage due to DMA transfer isn't interfering with the processor's ability to complete the workload. In some embodiments, an opportunistic transfer schedule may be found by solving an optimization problem.

Abstract: Techniques for computing matrix operations for arbitrarily large matrices on a finite-sized hybrid analog-digital matrix processor are described. Techniques for gain adjustment in a finite-sized hybrid analog-digital matrix processor are described which enable the system to obtain higher energy efficiencies, greater physical density and improved numerical accuracy. In some embodiments, these techniques enable maximization of the predictive accuracy of a GEMM-based convolutional neural network using low-precision data representations.

Abstract: Aspects relate to a photonic processing system, a photonic processor, and a method of performing matrix-vector multiplication. An optical encoder may encode an input vector into a first plurality of optical signals. A photonic processor may receive the first plurality of optical signals; perform a plurality of operations on the first plurality of optical signals, the plurality of operations implementing a matrix multiplication of the input vector by a matrix; and output a second plurality of optical signals representing an output vector. An optical receiver may detect the second plurality of optical signals and output an electrical digital representation of the output vector.

Abstract: A nano-opto-electro-mechanical System (NOEMS) phase shifter is described. The NOEMS may include a multi-slot waveguide structure suspended in air. The multi-slot waveguide structure may include three or more waveguides separated from each other by slots. The width of the slots may be sufficiently small to support slot modes, where a substantial portion of the mode energy is within the slots. For example, the slots may have widths less than 200 nm or less than 100 nm. The multi-slot waveguide structure may be disposed in a trench formed though the upper cladding of a substrate. An undercut may be formed under the multi-slot waveguide structure to enable free motion of the structure. NOEMS phase modulators of the types described herein may be used in connection with photonic processing systems, telecom/datacom systems, analog systems, etc.

Abstract: Low-noise optical differential receivers are described. Such differential receivers may include a differential amplifier having first and second inputs and first and second outputs, and four photodetectors. A first and a second of such photodetectors are coupled to the first input of the differential amplifier, and a third and a fourth of such photodetectors are coupled to the second input of the differential amplifier. The anode of the first photodetector and the cathode of the second photodetector are coupled to the first input of the differential amplifier. The cathode of the third photodetector and the anode of the fourth photodetector are coupled to the second input of the differential amplifier. The optical receiver may involve two stages of signal subtraction, which may significantly increase noise immunity.

Abstract: Photonic packages are described. One such photonic package includes a photonic chip, an application specific integrated circuit, and optionally, an interposer. The photonic chip includes photonic microelectromechanical system (MEMS) devices. A photonic package may include a material layer patterned to include recesses. The recesses are aligned with the photonic MEMS devices so as to form enclosed cavities around the photonic MEMS devices. This arrangement preserves the integrity of the photonic MEMS devices.

Abstract: Systems and methods for performing matrix operations using a path-number balanced optical network are provided. The optical network is formed as an array including active optical components and passive optical components arranged at a substantially central location of the array. The optical network includes at least NM active optical components which are used to implement a first matrix of any size N×M by embedding the first matrix in a second matrix of a larger size. The optical network performs matrix-vector and matrix-matrix operations by propagating one or more pluralities of optical signals corresponding to an input vector through the optical network.

Abstract: A training system for training a machine learning model such as a neural network may have a different configuration and/or hardware components than a target device that employs the trained neural network. For example, the training system may use a higher precision format to represent neural network parameters than the target device. In another example, the target device may use analog and digital processing hardware to compute an output of the neural network whereas the training system may have used only digital processing hardware to train the neural network. The difference in configuration and/or hardware components of the target device may introduce quantization error into parameters of the neural network, and thus affect performance of the neural network on the target device. Described herein is a training system that trains a neural network for use on a target device that reduces loss in performance resulting from quantization error.

Abstract: Systems and methods for increasing throughput of a photonic processor by using photonic degrees of freedom (DOF) are provided. The photonic processor includes a multiplexer configured to multiplex, using at least one photonic DOF, multiple encoded optical signals into a multiplexed optical signal. The photonic processor also includes a detector coupled to an output of an optical path including the multiplexer, the detector being configured to generate a first current based on the multiplexed optical signal or a demultiplexed portion of the multiplexed optical signal. The photonic processor further includes a modulator coupled to and output of the detector, the modulator being configured to generate a second current by modulating the first current.

Abstract: Aspects relate to a photonic processing system, a photonic processor, and a method of performing matrix-vector multiplication. An optical encoder may encode an input vector into a first plurality of optical signals. A photonic processor may receive the first plurality of optical signals; perform a plurality of operations on the first plurality of optical signals, the plurality of operations implementing a matrix multiplication of the input vector by a matrix; and output a second plurality of optical signals representing an output vector. An optical receiver may detect the second plurality of optical signals and output an electrical digital representation of the output vector.

Abstract: Hybrid analog-digital processing systems are described. An example of a hybrid analog-digital processing system includes photonic accelerator configured to perform matrix-vector multiplication using light. The photonic accelerator exhibits a frequency response having a first bandwidth (e.g., less than 3 GHz). The hybrid analog-digital processing system further includes a plurality of analog-to-digital converters (ADCs) coupled to the photonic accelerator, and a plurality of digital equalizers coupled to the plurality of ADCs, wherein the digital equalizers are configured to set a frequency response of the hybrid analog-digital processing system to a second bandwidth greater than the first bandwidth.

Abstract: Systems and methods for performing matrix operations using a path-number balanced optical network are provided. The optical network is formed as an array including active optical components and passive optical components arranged at a substantially central location of the array. The optical network includes at least NM active optical components which are used to implement a first matrix of any size N×M by embedding the first matrix in a second matrix of a larger size. The optical network performs matrix-vector and matrix-matrix operations by propagating one or more pluralities of optical signals corresponding to an input vector through the optical network.

Abstract: Low-noise optical differential receivers are described. Such differential receivers may include a differential amplifier having first and second inputs and first and second outputs, and four photodetectors. A first and a second of such photodetectors are coupled to the first input of the differential amplifier, and a third and a fourth of such photodetectors are coupled to the second input of the differential amplifier. The anode of the first photodetector and the cathode of the second photodetector are coupled to the first input of the differential amplifier. The cathode of the third photodetector and the anode of the fourth photodetector are coupled to the second input of the differential amplifier. The optical receiver may involve two stages of signal subtraction, which may significantly increase noise immunity.

Abstract: Photonic processors are described. The photonic processors described herein are configured to perform matrix-matrix (e.g., matrix-vector) multiplication. Some embodiments relate to photonic processors arranged according to a dual-rail architecture, in which numeric values are encoded in the difference between a pair optical signals (e.g., in the difference between the powers of the optical signals). Relative to other architectures, these photonic processors exhibit increased immunity to noise. Some embodiments relate to photonic processors including modulatable detector-based multipliers. Modulatable detectors are detectors designed so that the photocurrent can be modulated according to an electrical control signal. Photonic processors designed using modulatable detector-based multipliers are significantly more compact than other types of photonic processors.

Abstract: Photonic processors are described. The photonic processors described herein are configured to perform matrix-matrix (e.g., matrix-vector) multiplication. Some embodiments relate to photonic processors arranged according to a dual-rail architecture, in which numeric values are encoded in the difference between a pair optical signals (e.g., in the difference between the powers of the optical signals). Relative to other architectures, these photonic processors exhibit increased immunity to noise. Some embodiments relate to photonic processors including modulatable detector-based multipliers. Modulatable detectors are detectors designed so that the photocurrent can be modulated according to an electrical control signal. Photonic processors designed using modulatable detector-based multipliers are significantly more compact than other types of photonic processors.

Abstract: Photonic processors are described. The photonic processors described herein are configured to perform matrix multiplications (e.g., matrix vector multiplications). Matrix multiplications are broken down in scalar multiplications and scalar additions. Some embodiments relate to devices for performing scalar additions in the optical domain. One optical adder, for example, includes an interferometer having a plurality of phase shifters and a coherent detector. Leveraging the high-speed characteristics of these optical adders, some processors are sufficiently fast to support clocks in the tens of gigahertz of frequency, which represent a significant improvement over conventional electronic processors.

Abstract: Photonic processors are described. The photonic processors described herein are configured to perform matrix multiplications (e.g., matrix vector multiplications). Matrix multiplications are broken down in scalar multiplications and scalar additions. Some embodiments relate to devices for performing scalar additions in the optical domain. One optical adder, for example, includes an interferometer having a plurality of phase shifters and a coherent detector. Leveraging the high-speed characteristics of these optical adders, some processors are sufficiently fast to support clocks in the tens of gigahertz of frequency, which represent a significant improvement over conventional electronic processors.