Abstract: A switching regulator is configured to provide a regulated voltage to a load while maintaining a substantially maximum output current limit, the switching regulator having a loop gain. In accordance with one aspect the switching regulator comprises: a circuit for adjusting the maximum output current limit in response to a programmable signal independently of the loop gain. In accordance with another aspect, the switching regulator comprises: a resistance sensing element for providing the current output of the regulator, and having a resistance which varies with temperature; and a circuit for maintaining the output current limit at a level independent of the temperature of the sensing element. In addition, in accordance with one aspect, a method of providing a regulated voltage to a load is disclosed in which a substantially maximum output current limit of a switching regulator is maintained.

Abstract: A novel sampling system having a sampling device responsive to an analog input signal and a reference signal for providing corresponding charges. A switching circuit is provided to supply the input signal and the reference signal to the sampling device. The switching circuit is controlled to supply the input signal and the reference signal to the sampling device so as provide a substantially zero total charge taken by the sampling device from a source of the input signal. One application of the foregoing is in analog-to-digital conversion.

Abstract: An analog-to-digital converter according to the invention is provided. The analog-to-digital converter preferably includes an analog input signal, a first reference signal, a second reference signal, and a range compression signal. The range compression signal is preferably characterized by a magnitude greater than the first reference signal and smaller than the second reference signal. In addition, when the analog input signal is sampled N times and the range compression signal is sampled N1 times, a compression factor related at least in part to the ratio N1/(N+N1) is obtained.

Abstract: Switching regulator Burst Mode control circuitry is provided for limiting voltage overshoot at the output of a switching regulator operating in power saving Burst Mode. The Burst Mode control circuitry may include regulator load current sensing circuitry which may be operative to put and maintain the regulator in the SLEEP state when the load current amplitude is below a threshold. The control circuitry may also include gated over-voltage comparator circuitry operative to reduce regulator output overshoot and to eliminate erroneous deactivation of the regulator switch circuitry when the regulator is not operating in Burst Mode. The gated over-voltage circuitry may include a one-shot timer circuit.

Abstract: An analog-to-digital converter according to the invention is provided. The analog-to-digital converter preferably includes an analog input signal, a first reference signal, a second reference signal, and a range compression signal. The range compression signal is preferably characterized by a magnitude greater than the first reference signal and smaller than the second reference signal. In addition, when the analog input signal is sampled N times and the range compression signal is sampled N1 times, a compression factor that is based at least in part on N1/(N+N1) is obtained.

Abstract: A circuit for charging a photoflash that preferably reduces the average input to the switching regulator in an efficient fashion is provided. The regulator includes a transformer. The transformer includes a primary winding and a secondary winding. The switching regulator also includes a switch that closes at the beginning of a first portion of the switching cycle and opens at the end of the first portion of the switching cycle. The second portion of the cycle may be to allow the secondary winding to release current into the load. The switch is adapted to allow the current to build up in the primary winding when the switch is closed. The switching regulator may also include a delay circuit that introduces a delay between the end of the second portion of the cycle and the beginning of the first portion of the next switching cycle.

Abstract: Circuitry and methods for improved amplifiers with large bandwidth and constant gain are provided. The combination of a synthetic inductive drain load and a bridged-T matching network provide amplifiers that can drive a substantial capacitive load with the above mentioned improvements over prior amplifiers. Additionally, circuits presented allow for improved rise time and insensitivity to temperature variations.

Abstract: An analog-to-digital converter according to the invention is provided. The analog-to-digital converter preferably includes an analog input signal, a first reference signal, a second reference signal, and a range compression signal. The range compression signal is preferably characterized by a magnitude greater than the first reference signal and smaller than the second reference signal. In addition, when the analog input signal is sampled N times and the range compression signal is sampled N1 times, a compression factor that is based at least in part on N1/(N+N1) is obtained.

Abstract: An analog-to-digital converter according to the invention is provided. The analog-to-digital converter preferably includes an analog input signal, a first reference signal, a second reference signal, and a range compression signal. The range compression signal is preferably characterized by a magnitude greater than the first reference signal and smaller than the second reference signal. In addition, when the analog input signal is sampled N times and the range compression signal is sampled N1 times, a compression factor related at least in part to the ratio N1/(N+N1) is obtained.

Abstract: Light emitting elements with preselected or adjustable impedance characteristics are provided. Embodiments using a preselected impedance characteristic obtain significant performance benefits compared to the prior art. Embodiments having an adjustable impedance may alter the impedance associated with the light emitting component such that it has a substantially constant resistive or reactive impedance that improves certain performance attributes. This solution virtually eliminates the need for external compensation components and relieves the burden of impedance matching and circuit specialization from the driver circuit.

Abstract: The present invention provides a capacitor charging circuit that efficiently charges capacitive loads. In particular, circuits and techniques are preferably provided for using current from both the primary and secondary windings of a transformer to control ON-time and OFF-time of a switch. This arrangement preferably yields an adaptable ON-time and adaptable OFF-time switch that is capable of rapidly charging capacitor loads ranging from as low as zero volts to several hundred volts. The output voltage is preferably measured indirectly to prevent unnecessary power consumption. In addition, control circuitry can be provided to conserve power by ceasing the delivery of power to the capacitor load once the desired output voltage is reached. Control circuitry preferably operates an interrogation timer that periodically activates the power delivery cycle to maintain the capacitor output load in a constant state of readiness.

Abstract: An adaptive current reversal comparator for synchronous switching regulator comparison circuit for use in a switching regulator is provided. The comparison circuit includes a voltage offset that is used at least in part to compensate for a propagation delay of the comparison circuit. The switching regulator includes an inductor and a synchronous transistor. The comparison circuit also includes a timing circuit that provides a threshold amount of time and an offset adjustment circuit. The offset adjustment circuit preferably decreases the voltage offset of the comparison circuit when a synchronous transistor control signal transitions to an OFF state more than the threshold amount of time prior to the discharge of an inductor. The comparison circuit also increases the voltage offset of the comparison circuit when the synchronous control signal transitions to an OFF state more than the threshold amount of time following the discharge of the inductor.

Abstract: An adaptive current reversal comparator for synchronous switching regulator comparison circuit for use in a switching regulator is provided. The comparison circuit includes a voltage offset that is used at least in part to compensate for a propagation delay of the comparison circuit. The switching regulator includes an inductor and a synchronous transistor. The comparison circuit also includes a timing circuit that provides a threshold amount of time and an offset adjustment circuit. The offset adjustment circuit preferably decreases the voltage offset of the comparison circuit when a synchronous transistor control signal transitions to an OFF state more than the threshold amount of time prior to the discharge of an inductor. The comparison circuit also increases the voltage offset of the comparison circuit when the synchronous control signal transitions to an OFF state more than the threshold amount of time following the discharge of the inductor.

Abstract: Novel system and methodology for sampling analog input signals to reduce an average common-mode input current caused by unbalanced nodes of an input signal source. An analog-to-digital (A/D) conversion system for converting an analog input signal supplied by a signal source having first and second nodes may have a first sampling circuit coupled to the first node for sampling the input signal with respect to a reference signal and configured so as to provide a substantially zero total charge taken from the first node during a first sampling process, and a second sampling circuit coupled to the second node for sampling the input signal with respect to the reference signal and configured so as to provide a substantially zero total charge taken from the second node during a second sampling process. In response to first and second output signals respectively produced by the first and second sampling circuits, an output circuit may provide common-mode rejection.

Abstract: A novel sampling system having a sampling device responsive to an analog input signal and a reference signal for providing corresponding charges. A switching circuit is provided to supply the input signal and the reference signal to the sampling device. The switching circuit is controlled to supply the input signal and the reference signal to the sampling device so as provide a substantially zero total charge taken by the sampling device from a source of the input signal. One application of the foregoing is in analog-to-digital conversion.

Abstract: A novel sampling system having a sampling device responsive to an analog input signal and a reference signal for providing corresponding charges. A switching circuit is provided to supply the input signal and the reference signal to the sampling device. The switching circuit is controlled to supply the input signal and the reference signal to the sampling device so as provide a substantially zero total charge taken by the sampling device from a source of the input signal. One application of the foregoing is in analog-to-digital conversion.

Abstract: A novel sampling system having a sampling device responsive to an analog input signal and a reference signal for providing corresponding charges. A switching circuit is provided to supply the input signal and the reference signal to the sampling device. The switching circuit is controlled to supply the input signal and the reference signal to the sampling device so as provide a substantially zero total charge taken by the sampling device from a source of the input signal. One application of the foregoing is in analog-to-digital conversion.

Abstract: Circuits and methods for interconnecting a live backplane and at least one I/O card are provided. This invention provides interconnection circuitry that utilizes buffer circuitry to connect the data and clock busses of the backplane to the data and clock busses of the I/O card in a “hot-swappable” fashion. Buffer circuitry also isolates the capacitance associated with the backplane from the capacitance associated with the I/O card. For example, when at least one signal is driven from the backplane to the I/O card, the signal need only overcome the capacitance associate with the backplane. Conversely, when at least one signal is driven from the I/O card to the backplane, the signal need only overcome the capacitance associated with the I/O card. Hence, this capacitive isolation facilitates signal propagation between the backplane and the I/O card.

Abstract: Bidirectional power conversion systems provide the ability to change power attributes to and from a component. Current bidirectional power conversion systems use a unidirectional power converter for each direction. The integration of the two normally independent power converters results in a bidirectional power converter with nearly half the size, weight, volume, cost and complexity. Described are embodiments of bidirectional power conversion systems that allow power transfer between two or more components without requiring the use of separate unidirectional power converters.

Abstract: Switching regulator circuits and methods are provided for regulating output voltage that include an adjustable minimum peak inductor current level for Burst Mode in current-mode DC-DC regulators. Minimum peak inductor current level control is achieved during Burst Mode by allowing external control for adjusting the burst threshold level. A single pin can be used to distinguish between forced continuous and Burst Mode as well as set the burst threshold level during Burst Mode, or an alternate method of setting a variable burst threshold level can be implemented in which two pins are used, one for selecting the mode of operation and the other for setting the burst threshold level during Burst Mode. The above principles can be applied to both step-up and step-down regulator circuit configurations, as well as both synchronous switching regulators and non-synchronous switching regulators.