Abstract: A clock frequency division circuit receives delay value, synchronization signal, and external clock signal of a given frequency. The clock division circuit includes (a) a decode circuit receiving delay value and providing set of initial count values; (b) one or more counters each receiving input clock signal derived from the external clock signal and providing frequency divided output signal having a frequency a fraction of the given frequency, and each receiving a corresponding one of the initial count values, and wherein, subsequent to detecting a transition in the synchronization signal, each counter provides transition in the frequency divided output signal after a time period represented by corresponding initial count value; and (c) synchronization circuit that is reset by the synchronization signal, the synchronization circuit providing a gating signal enabling output of the frequency divided output signal after expiration of initial count value. The one or more counters may be cascaded.

Abstract: In a variable gain amplifier, a base of a bipolar first transistor receives a first differential input signal. The emitter of the first transistor is connected in series between a first resistor and a MOSFET coupled to ground. An output of the amplifier is a current through the collector. The conductivity of the MOSFET controls a gain of the amplifier. A bipolar second transistor receives a second differential input signal, and the second transistor provides a modulated gate voltage to the MOSFET. The drain voltage of the MOSFET is modulated by the first differential input signal and thus undesirably generates distortion. To reduce the distortion, the modulated gate voltage causes the AC component for a certain DC voltage at the drain of the MOSFET to be lowered, improving linearity. Since no current source is used, the amplifier has a large headroom, allowing operation using a low operating voltage.

Abstract: A Power Over Ethernet (PoE) system includes Power Sourcing Equipment (PSE) providing data and voltage over Ethernet wires to a Powered Device (PD). Instead of the conventional detection and classification routine being performed every time the system is powered up, the pertinent data to determine whether to apply PoE to the PD is stored in a memory in the PSE. The memory is accessed by a controller in the PSE when the PSE is powered up. Therefore, a time-consuming detection and classification routine does not have to be performed each time the system is powered up. The system is particularly useful in automobiles where the particular PDs and PSEs are predetermined. The PoE data may be obtained the first time the system is powered up or may be stored in the memory when the PSE is designed or fabricated.

Abstract: A differential amplifier may, when connected to a positive or negative supply voltage and to a ground voltage, provide a differential pair of outputs signals at a differential output that are an amplification of a differential pair of input signals at a differential input. A differential input stage may receive the differential pair of input signals from the differential input and may include a first transistor associated with one of the input signals and a second transistor associated with the other input signal. A differential output stage may generate the differential pair of output signals at the differential output and may include a third transistor associated with one of the output signals and a fourth transistor associated with the other output signal. The first, second, third, and fourth transistors may be all P type or all N type.

Abstract: A converter may generate an analog output that is representative of a time-encoded signal. The circuit may include an input port receiving the time-encoded signal; a time-encoded to digital converter coupled to the input port; and a digital-to-analog converter coupled to the time-encoded to digital converter.

Abstract: In one embodiment, a regulator circuit for generating a regulated output voltage Vout has an error amplifier using a pair of bipolar transistors at its front end. The error amplifier compares the regulated output voltage to a reference voltage Vref. A precision current source draws a first current through a user-selected set resistance to generate the desired Vref. The regulator circuit controls a power stage to cause Vout to be equal to Vref. The base current into one of the bipolar transistors normally distorts the current through the set resistance. A base current compensation circuit is coupled to the current source to adjust the first current by a value equal to the base current to offset the base current. Therefore, Vref is not affected by the base current. The error amplifier may be in a linear regulator or a switching regulator. The compensation circuit may be used in other applications.

Abstract: A converter has a boost portion and a buck portion. The boost portion supplies a boosted voltage and includes a first inductor having a first end coupled to the input terminal, a first switch coupled to a second end of the first inductor to charge the first inductor when the first switch is in its on-state, and a first capacitor for being charged to the boosted voltage. The buck portion supplies an output voltage to a load that is less than the boosted voltage and includes a second inductor in series with the load, and a second switch in series with the second inductor and the load to charge the second inductor during an on-state of the second switch. A single controller IC receives feedback signals and controls the switches to have the same duty cycle to achieve a regulated load current or voltage with low EMI.

Abstract: A power converting system produces an input signal regulated with respect to an input signal. The power converting system has a first inductive element having a first node coupled to an input node, and a second inductive element having a first node coupled to an output node. A first switching element is coupled to a second node of the first inductive element. A first capacitive element is coupled between the second node of the first inductive element and of the second inductive element. A control circuit sets a duty cycle of the first switching element to a first value for providing the output signal of a first polarity responsive to the input signal of the first polarity, and to set the duty cycle of the first switching element to a second value for providing the output signal of a second polarity responsive to the input signal of the first polarity.

Abstract: A multistage amplifier may include a multistage amplifier circuit and a resistive voltage divider network. The multistage amplifier circuit may have multiple transconductance input stages, each of which may have differential inputs and an adjustable tail current input that controls the amount of the transconductance of the input stage. The resistive voltage divider network may control the closed loop gain of the multistage amplifier circuit and include multiple resistors that provide different voltage divider ratios at different points. Each point may be connected to one of the transconductance input stages. Adjustment of tail currents at the tail current inputs may control the degree to which each point affects the closed loop gain of the multistage amplifier.

Abstract: An RMS-DC converter includes a chopper-stabilized square cell that eliminates offset, thus enabling high-bandwidth operation. The chopper-stabilized offset requires only a small portion of the circuitry (i.e., a single component square cell) which operates at high frequencies, and is amenable to using high-bandwidth component square cells. Using the chopping technique minimizes required device sizes without compromising an acceptable square cell dynamic range, thereby maximizing the square cell bandwidth. The RMS-DC converter consumes less power than conventional RMS-to-DC converters that requires a high-frequency variable gain amplifier.

Abstract: An analog-to-digital converter (ADC) system and method. The ADC system in accord with one embodiment includes a sampling digital-to-analog converter configured to sample a combination of an analog signal value and an analog dither value, and a control circuit comprising a mismatch-shaping encoder. The control circuit is configured to sequentially apply a plurality of digital codes to the sampling digital-to-analog converter during an analog-to-digital conversion operation to derive a digital code representing the combination of the analog signal value and the analog dither value. Several embodiments are presented.

Abstract: Apparatus and method for a polarity independent step-up converter capable of operating with ultra low input voltage. The step-up converter as disclosed herein receives an input source having a variable polarity and includes a first core circuit coupled to the input source and an output of the step-up converter and a second core circuit coupled to the input source and the output of the step-up converter. The first core circuit is configured to be active for a first input voltage polarity to output a first step-up voltage and the second core circuit is configured to be active for a second input voltage polarity to output a second step-up voltage.

Abstract: A broadband radio frequency, microwave, or millimeter mixer system may include a balun and a mixer. The balun may have an unbalanced port; a balanced port; a first and a second inductor tightly and inversely magnetically coupled to one another; and a third inductor which is not magnetically coupled to the first or the second inductors. The mixer may be connected to the balanced port of the balun. The balun, including its three inductors, and the mixer may all be integrated onto a single substrate that forms an integrated circuit.

Abstract: An auto-resonant driver for a transmitter inductor drives the inductor at an optimal frequency for maximum efficiency. The transmitter inductor is magnetically coupled, but not physically coupled, to a receiver inductor, and the current generated by the receiver inductor is used to power a load. The system may be used, for example, to remotely charge a battery (as part of the load) or provide power to motors or circuits. A feedback circuit is used to generate the resonant driving frequency. A detector in the transmit side wirelessly detects whether there is sufficient current being generated in the receiver side to achieve regulation by a voltage regulator powering the load. This point is achieved when the transmitter inductor peak voltage suddenly increases as the driving pulse width is ramped up. At that point, the pulse width is held constant for optimal efficiency.

Abstract: A tunable and trimmable analog filter may include a tunable analog filter and a trimming circuit. The tunable analog filter may set the frequency of a characteristic of the tunable analog filter based on a digital tuning signal that is indicative of a desired frequency of the characteristic. However, the tunable analog filter may contain components having values that deviate from specified values due to var during manufacture of the tunable analog filter. The value deviations can cause the frequency of the characteristic not to precisely match the frequency indicated by the digital tuning signal. The trimming circuit may include a non-volatile memory that contains data. The trimming circuit may receive tuning information indicative of a desired frequency for the characteristic of the tunable analog filter.

Abstract: A maximum voltage selection circuit may include multiple inputs, each for receiving a different input voltage, an output for delivering the highest of the input voltages, and a voltage selection circuit. The voltage selection circuit may automatically select the input having the largest voltage magnitude, automatically deliver the voltage at the selected input to the output, and not draw quiescent operating current from any of the inputs.

Abstract: A frequency synthesizer directly generates phase modulated radio-frequency (RF) signals. The frequency synthesizer includes a voltage controlled oscillator (VCO) producing a synthesized frequency signal having a frequency controlled based on a signal received at an input of the VCO. A digitally adjustable frequency divider produces a reduced frequency signal from the synthesized frequency signal. A phase digital-to-analog converter (DAC) produces a delayed version of a timing signal (e.g., the reduced frequency signal, or a reference clock signal) that is delayed according to a digital control signal. A phase detector (PD) produces a phase control signal from the reduced frequency signal and/or the delayed timing signal. A digital signal converter controls the digitally adjustable frequency divider and the phase DAC so as to cause a phase or frequency of the synthesized frequency signal output by the VCO to track a desired phase or frequency trajectory encoded in a digital signal.

Abstract: A sampling circuit may include a sampling capacitance, an electronic sampling switch, and a switch controller. The electronic sampling switch may have a control input that controls whether the electronic sampling switch is in a sample state or a hold state. The electronic sampling switch may connect the sampling capacitance to an input signal while in the sample state and disconnect the sampling capacitance from the input signal while in the hold state. The switch controller may control the control input to the electronic sampling switch so as to cause the electronic sampling switch to be in the sample state during one period and the hold state during another period. While in the sample state, the switch controller may cause the impedance of the electronic sampling switch that is seen by the input signal to be substantially independent of the voltage of the input signal.

Abstract: A forward converter has a primary side containing a PWM controller for controlling switching of a power switch and has a secondary side coupled to the primary side via a transformer. The secondary side includes a forward transistor and a catch transistor. A secondary side switch controller controls switching of the forward transistor and the catch transistor without communication from the primary side. The secondary side switch controller detects the rising and falling of the voltages at the ends of the secondary winding to control the switching of the forward and catch transistors. A delay locked loop (DLL) is provided in the secondary side switch controller that turns on the catch transistor when the power switch is turned off and turns off the catch transistor at a predetermined time before the power switch is turned on. A separate circuit controls the catch transistor during a discontinuous mode.

Abstract: A system for monitoring an energy storage system composed of multiple cells connected in series has a chain of monitors including at least first and second monitors. The first monitor is configured for monitoring at, least a first cell in the energy storage system to produce first monitored data. The second monitor is configured for monitoring at least a second cell in the energy storage system to produce second monitored data. The first monitor is further configured for transferring the first monitored data to the second monitor for delivery to a controller.