Abstract: An electronic circuit comprises an analog-to-digital converter (ADC) circuit. The ADC circuit includes a pre-amplifying transistor and a quantizer circuit. The pre-amplifying transistor includes a base, an emitter and a collector. The pre-amplifying transistor is configured to receive an input voltage at the base that varies logarithmically; and produce an output voltage at the collector according to a comparison of a reference voltage and a difference between the input voltage and a voltage at the emitter. The quantizer circuit is operatively coupled to the pre-amplifying transistor and is configured to generate a digital value for the input voltage using the output voltage produced by the pre-amplifying transistor.

Abstract: A hybrid power converter includes a switching circuit, an LC circuit, and a detection circuit. The switching circuit includes three or more switching transistors in series that may turn on or off according to a switching cycle to generate a series of voltage pulses at an output port across one of the switching transistors. The LC circuit may be coupled to the output port of the switching circuit to receive the series of pulses and to generate an inductor current in the LC circuit. The inductor current may charge a capacitor of the LC circuit to generate an output voltage of the hybrid power converter. The detection circuit may be coupled to the switching circuit and may generate a low frequency portion of the inductor current based on one or more currents of the switching transistors to adjust the switching cycle based at least on the low frequency portion.

Abstract: A switching power converter circuit comprises an inductor arranged to receive input energy from an input circuit node; a switch circuit coupled to the inductor; a load current sensing circuit element coupled to a regulated circuit node and an output circuit node; a compensation circuit coupled to a compensation circuit node; a control circuit coupled to the compensation circuit node and the switch circuit, the control circuit configured to modulate activation of the switch circuit to regulate a voltage at the regulated circuit node; and a feedforward circuit coupled to the load current sensing circuit element and the compensation circuit, and configured to adjust modulation of the switch circuit according to sensed load current.

Abstract: Chopper amplifiers with high pass filters for suppressing chopping ripple are provided herein. In certain embodiments, a chopper amplifier includes an input chopping circuit, an amplification circuit, a low frequency content detection circuit, and an output chopping circuit electrically connected in a cascade. The low frequency content detection circuit operates in combination with a transconductance or other gain circuit as a high pass filter that filters input offset voltage and/or low frequency noise of the amplification circuit, thereby suppressing output chopping ripple from arising.

Abstract: In a PoE system, DC power is transmitted over two wire pairs. The primary winding of an isolation transformer is connected across the differential I/O terminals of a first PHY (a transceiver). A positive voltage output of a power supply is connected to a center tap of the secondary winding, and the secondary winding is coupled across a first wire pair. In this way, differential data and DC power is supplied to the first wire pair. A CMC is connected between the secondary winding and an autotransformer which is also connected across the first wire pair. A center tap of the autotransformer is also connected to the positive voltage output of the power supply, so that the current to the powered device is shared by the isolation transformer and the autotransformer. A similar circuit, with a second PHY, is used for the DC power return path.

Abstract: A PoDL system conducts differential data and DC power over the same wire pair, and various DC coupling techniques are described that improve DC voltage coupling while attenuating AC common mode noise. Pairs of differential mode chokes (DMCs) are used to share current supplied by a power supply. In one embodiment, one DMC is coupled to the line side of a common mode choke (CMC), and one DMC is coupled to the PHY side of the CMC. The line-side DMC has windings that are loosely magnetically coupled so that DMC does not present a very low impedance to AC common mode noise on the wires. Therefore, the performance of the wires' RC termination circuitry is not adversely affected by the line-side DMC when minimizing reflections of common mode signals. The DMCs may use the same magnetic core, and the CMC may be series CMCs that used the same magnetic core.

Abstract: A transceiver capable of common mode operating range and output voltage tolerance set by an isolation boundary and not limited by the device type used in the circuitry. The subject technology is a powered isolated transceiver, where the isolated generated supply and ground nodes are concealed and thus do not participate in tests that stress electrostatic discharge (ESD)/electrical overstress (EOS) or voltage tolerance. The architecture of the subject technology has the advantage of extremely high common mode performance and robust performance using low voltage devices and simplified architecture, which in turn provides less capacitive loading, faster operation, less expensive die development, electromagnetic interference (EMI) advantages, and simple active termination. The subject technology includes an isolation architecture that can be used in environments where isolation is used but is also advantageous in systems without the need for isolation.

Abstract: Techniques for operating a power supply under light load conditions are provided. In an example, a frequency of an oscillator can be adjusted based on a feedback signal indicative of a voltage error of the power supply when the feedback signal falls below a first threshold. In certain examples, a peak inductor current command can be kept constant and a slope compensation ramp can be based on the frequency of the oscillator when the feedback signal falls below the first threshold. In some examples, various circuits of the power supply can be disabled when the feedback signal further falls below a second threshold. The feedback signal can be indicative of a load on the power supply.

Abstract: A wireless power transfer system may wirelessly transmit and receive power. A transmitting coil may wirelessly transmit the power. A receiving coil may be magnetically but wirelessly coupled to the transmitting coil and may wirelessly receive the power and generate an AC input voltage. A rectifier may rectify the AC input voltage. A capacitance may filter the rectified AC input voltage. An electronic switch may be connected in series between the rectified AC input voltage and an output. A load may be connected to the output. A controller may open and close the electronic switch so as to cause the output to be at a constant DC voltage, notwithstanding variations in the load.

Abstract: A power divider/combiner circuit with coupled inductors is provided. With coupled inductors, the new circuit topology exhibits broader bandwidth for insertion loss, port matching and isolation compared with traditional power divider/combiner circuit topologies. The coupled inductors can be implemented for single-stage low-pass networks, multi-stage low-pass networks, or multi-stage wide-band networks. For example, the power divider/combiner circuit includes a first coupled inductor circuit coupled to an input terminal that provides a first signal path to a first output terminal, and a second coupled inductor circuit coupled to the input terminal that provides a second signal path to a second output terminal. Each of the coupled inductor circuits include multiple inductors that are tightly and positively magnetically coupled to one another.

Abstract: In a PoDL system, where DC power and differential data are supplied over the same conductors between a PSE and a PD, a low-power test is first performed to determine the conductor resistance. The PSE and PD are connected to the conductors via DC-coupling inductors that block the data signals. Such inductors have a DC resistance (DCR). To avoid the DCR of the PD inductors being included in the resistance test of the conductors and to avoid the requirement of additional pins for kelvin sensing, the PD includes a MOSFET switch connected across the conductors on the line-side of the PD inductors. The PSE applies a current pulse of a known value to one of the conductors while the MOSFET switch is temporarily closed. The PSE measures the resulting voltage across the wires and uses Ohm's law to more accurately calculate the resistance of the conductors.

Abstract: In a Power over Data Lines (PoDL) system that conducts differential data and DC power over the same wire pair, various DC coupling techniques are described that improve DC voltage coupling while attenuating AC common mode noise. Pairs of differential mode chokes (DMCs) are used to share current supplied by a single phase or multi-phase power supply. In one embodiment, one DMC is coupled to the line side of a common mode choke (CMC), and one DMC is coupled to the PHY side of the CMC. The line-side DMC has windings that are loosely magnetically coupled so that DMC does not present a very low impedance to AC common mode noise on the wires. Therefore, the performance of the wires' RC termination circuitry is not adversely affected by the line-side DMC when minimizing reflections of common mode signals.

Abstract: A first circuit board includes a master device and slave devices communicating with each other via a local first I2C bus. To allow I2C networks to communicate with each other over long distances, such as up to 1200 meters, a first interface device converts the I2C data signals to encoded differential data over a twisted wire pair. A second interface device on a remote circuit board converts the differential data to data and clock signals on its local second I2C bus coupled to other slave devices on the same board. This is equivalent to the two boards sharing the same I2C bus. The interface devices pull down the serial clock line (SCL) in their local I2C bus while waiting for data, such as an acknowledge bit. The master device generates the clock signal for its local I2C bus, and the remote interface device generates the clock signal for its local I2C bus.

Abstract: In a PoDL system, a PHY has its I/O terminals coupled to a wire pair via a galvanic isolation transformer and a CMC. Thus, DC power and common mode noise are blocked from the PHY inputs. One end of the secondary winding of the transformer is directly coupled to one winding of the CMC. A DC power supply has its positive voltage terminal directly coupled to the other end of the secondary winding and has its other output terminal (e.g., ground) directly coupled to the other winding of the CMC. An AC-coupling capacitor is coupled between the two outputs of the power supply. Differential signals are applied across the secondary winding to couple the differential signals to the PHY, while the secondary winding conducts the DC voltage to one of the wires (via the CMC), and the ground is coupled to the other one of the wires (via the CMC).

Abstract: In a system and method for correcting a stress-impaired signal in a circuit, a calibration circuit produces a first calibrated voltage based on a base-emitter voltage of one or more pnp transistors, a second calibrated voltage based on a base-emitter voltage of one or more npn transistors, and a voltage proportional to absolute temperature. A set of reference values are generated based on these voltages. A gain correction factor is calculated based on a function of the set of reference values and a set of temperature-dependent values, and the stress-impaired signal is corrected based on the gain correction factor.

Abstract: A hybrid power converter includes a primary switching circuit, an LC circuit, and a secondary switching circuit. The primary switching circuit includes three or more switching transistors in series that may turn on or off according to a switching cycle to generate a series of voltage pulses at a connecting node between two switching transistors. The LC circuit may be coupled via the to the secondary switching circuits to the connecting node of the primary switching circuit. The LC circuit may receive, from the primary switching circuit, a series of pulses via the secondary switching circuits and may generate an inductor current in the LC circuit. The inductor current may charge a capacitor of the LC circuit to generate an output voltage of the hybrid power converter. The output voltage may have a reverse polarity with respect to an input voltage that may be coupled to the primary switching circuit.

Abstract: Various examples described herein are directed to a differential controller including a first regulator and a second regulator. The first regulator receives a first regulator control signal and generates a first regulator output signal. The second regulator receives a second regulator control signal and generates a second regulator output signal. A load is electrically coupled between a first regulator output and a second regulator output. The load current and voltage are based on a difference between the first regulator output and the second regulator output. A current sensor generates a load current signal that describes a load current at the load. A first amplifier generates the first regulator control using the load current signal and a control signal. A second amplifier generates the second regulator control signal using the first regulator input voltage and a common mode voltage.

Abstract: Methods and systems of synchronizing events using a plurality of sequencing controllers are provided. For each sequencing controller, a serial communication bus (SCB) is monitored for a first reference level. Upon identifying that the SCB is at the first reference level for a predetermined period, a bit sequence indicative of an event position is broadcast to be arbitrated on the SCB. The SCB is monitored for the arbitrated bit sequence. Upon determining that the arbitrated bit sequence corresponds to the bit sequence of the event position, an event corresponding to the event position is enabled.

Abstract: The subject technology provides for removing a source of delay in a phase-locked loop (PLL) by causing the output rising edge to occur at the same time as the input rising edge. The subject technology replicates the amount of delay experienced along an input reference signal path to the PLL as close as possible using a same circuit configuration and bias circuits as in the input reference signal path. For example, a timing alignment circuit containing a replica circuit adds compensation delay to a negative feedback loop signal to match the feedback loop delay with the reference path delay. The delay of the reference signal path is estimated and added into the replica circuit. The delay characteristics of these two paths negate one another such that the phases of the input reference signal and the feedback loop signal become phase-locked at the input to the PLL.

Abstract: A stacked package configuration is described that includes a bottom package and an upper package. The bottom package includes a substrate having a top surface with first circuitry and metal first pads. A molded layer is then formed over the substrate. Holes through the molded layer are then laser drilled to expose the first pads. The holes and first pads align with leads of an upper package, which contains further circuit components. The holes are then partially filled with a solder paste. A thermal epoxy is applied between the molded layer and the upper package. The leads of the upper package are then inserted into the holes, and the solder paste is reflowed to electrically, thermally, and mechanically connect the upper package to the bottom package. The reflow heat also cures the epoxy. A ball grid array is then formed on the bottom of the substrate.