Abstract: A surge protection apparatus may include an input terminal; an output terminal, the output terminal electrically coupled to the input terminal; a ground terminal, the ground terminal electrically coupled to the input terminal and output terminal: a positive temperature coefficient (PTC) fuse, the PTC fuse connected in electrical series between the input terminal and output terminal; a crowbar device, the crowbar device electrically connected to the ground terminal and output terminal, wherein the crowbar device is in electrical series with the PTC fuse between the input terminal and ground terminal; and a central frame portion, the central frame portion electrically coupled to the input terminal, output terminal and ground terminal, wherein the crowbar device is disposed on a first side of the central frame portion and the PTC fuse is disposed on a second side of the central frame portion, opposite the first side.

Abstract: Provided herein are semiconductor packages with improved clamps. In some embodiments, a semiconductor package may include a housing having a wall extending from a main body, and a set of support walls extending from the wall. The semiconductor package may further include a clamp extending between the set of support walls, the clamp having a first planar section coupled to a first support wall of the set of support walls, a second planar section coupled to a second support wall of the set of support walls, and a third planar section between the first and second planar sections. The third planar section may include an opening operable to receive a fastener, and a plurality of stress relief openings.

Abstract: In one embodiment, an asymmetric TVS device may include a semiconductor substrate, comprising an inner region, the inner region having a first polarity, and a first surface region, disposed on a first surface of the semiconductor substrate, the first surface region comprising a second polarity, opposite the first polarity. The asymmetric TVS device may also include a second surface region, comprising the second polarity, and disposed on a second surface of the semiconductor substrate, opposite the first surface, wherein the first surface region comprises a first dopant concentration, and wherein the second surface region comprises a second dopant concentration, greater than the first dopant concentration.

Abstract: An apparatus may include a transient voltage suppression (TVS) device array coupled to a first input terminal and a second input terminal; and a linear regulator module having a pair of inputs connected to a respective pair of outputs of the TVS device array, wherein the TVS device array includes at least one TVS diode is connected between a first output and second output of the pair of outputs to generate a first clamping voltage signal, and wherein the linear regulator module is configured to generate a second clamping voltage signal having a second clamping voltage independent of a first clamping voltage of the first clamping voltage signal received from the TVS device array.

Abstract: Aspects of the present disclosure include one or more semiconductor electrostatic discharge protection devices. At least one embodiment includes a semiconductor electrostatic discharge device with one or more fingers divided into two segments with alternating p-diffusion and n-diffusion regions, with each region being associated with at least one of a portion of a diode and/or silicon-controlled rectifier (SCR).

Abstract: In one embodiment, an overvoltage protection device may include a metal oxide varistor (MOV) having a first surface and a second surface; a semiconductor substrate having a first outer surface and a second outer surface and comprising a semiconductor crowbar device comprising a plurality of semiconductor layers arranged in electrical series to one another, the semiconductor substrate being disposed on a first side of the metal oxide varistor; a conductive region disposed between the second surface of the MOV and the first outer surface of the semiconductor substrate; a first electrical contact disposed on the first surface of the MOV; and a second electrical contact disposed on the second outer surface of the semiconductor substrate.

Abstract: In one embodiment, an overvoltage protection device may include a metal oxide varistor (MOV) having a first surface and a second surface; a semiconductor substrate having a first outer surface and a second outer surface and comprising a semiconductor crowbar device comprising a plurality of semiconductor layers arranged in electrical series to one another, the semiconductor substrate being disposed on a first side of the metal oxide varistor; a conductive region disposed between the second surface of the MOV and the first outer surface of the semiconductor substrate; a first electrical contact disposed on the first surface of the MOV; and a second electrical contact disposed on the second outer surface of the semiconductor substrate.

Abstract: An apparatus may include a transient voltage suppression (TVS) device array coupled to a first input terminal and a second input terminal; and a linear regulator module having a pair of inputs connected to a respective pair of outputs of the TVS device array, wherein the TVS device array includes at least one TVS diode is connected between a first output and second output of the pair of outputs to generate a first clamping voltage signal, and wherein the linear regulator module is configured to generate a second clamping voltage signal having a second clamping voltage independent of a first clamping voltage of the first clamping voltage signal received from the TVS device array.

Abstract: A power switching device may include a semiconductor substrate and a body region comprising an n-type dopant, the body region disposed in an inner portion of the semiconductor substrate; a first base layer disposed adjacent a first surface of the semiconductor substrate, the first p-base layer comprising a p-type dopant; a second base layer disposed adjacent a second surface of the semiconductor substrate, the second base layer comprising a p-type dopant; a first emitter region, disposed adjacent the first surface of the semiconductor substrate, the first emitter region comprising a n-type dopant; a second emitter-region, disposed adjacent the second surface of the semiconductor substrate, the second emitter-region comprising a n-type dopant; a first field stop layer arranged between the first base layer and the body region, the first field stop layer comprising a n-type dopant; and a second field stop layer arranged between the second base layer and the body region, the second field stop layer comprising a n

Abstract: In one embodiment, an overvoltage protection device (100) may include a crowbar device (106), where the crowbar device (106) includes a first crowbar terminal (115), the first crowbar terminal (115) connected with a first external voltage line (102). The overvoltage protection device (100) may further include a transient voltage suppression (TVS) device (108), where the TVS device (108) includes a second TVS terminal (121), the second TVS terminal (121) connected with a second external voltage line (104). The crowbar device (106) and the TVS device (108) may be arranged in electrical series between the first crowbar terminal (115) and the second TVS terminal (121).

Abstract: An overvoltage protection device (100) may include a metal oxide varistor (MOV) (102) having a first surface (114) and a second surface (116); a semiconductor substrate (202) having a first outer surface (126) and a second outer surface (128) and comprising a semiconductor crowbar device (104) comprising a plurality of semiconductor layers arranged in electrical series to one another, the semiconductor substrate (202) being disposed on a first side of the metal oxide varistor (102), a conductive region (124) disposed between the second surface (116) of the MOV (102) and the first outer surface (126) of the semiconductor substrate (202); a first electrical contact (120) disposed on the first surface (114) of the MOV (102); and a second electrical contact (122) disposed on the second outer surface (128) of the semiconductor substrate (202).