Abstract: Systems and methods for simultaneous multi-channel off-axis holography are described. Multi-channel imaging systems can include a light system including a plurality of light sources configured to generate illumination and reference beams at a plurality of wavelengths, an illumination system configured to illuminate a target object with the illumination beams, an optical assembly configured to receive a reflected target beam and condition the target beam for recording at an optical imaging system, and a reference system configured to propagate the reference beams to the optical imaging system. The reference beams are interfered with the target beam at the optical imaging system to create interference patterns, which can be recorded in a collective image having a plurality of side lobes. Holographic information in the side lobes can be combined to generate 3D images having a substantially reduced signal to noise ratio.
Abstract: A media application selects, from a collection of images associated with a user account, candidate pairs of images, where each pair includes a first static image and a second static image from the user account. The media application applies a filter to select a particular pair of images from the candidate pairs of images. The media application generates, using an image interpolator, one or more intermediate images based on the particular pair of images. The media application generates a video that includes three or more frames arranged in a sequence, where a first frame of the sequence is the first static image, a last frame of the sequence is the second static image, and each of the one or more intermediate images is a corresponding intermediate frame of the sequence between the first frame and the last frame.
Type:
Grant
Filed:
December 30, 2021
Date of Patent:
February 6, 2024
Assignee:
Google LLC
Inventors:
Janne Kontkanen, Jamie Aspinall, Dominik Kaeser, Navin Sarma, Brian Curless, David Salesin
Abstract: An improved mobile apparatus for sterilizing surgical trays serves as a self-contained autoclave, allowing sterilization of the interior of the apparatus and its contents. A method of sterilization using the apparatus is presented as well. By means of a dedicated transfer and storage system, the apparatus, integrable with respect to a transfer cart and a lift device, may be moved easily between a location of sterilization, a storage area, and an operating room, and more than one such apparatus may be stacked vertically for storage to enhance storage efficiency.
Type:
Grant
Filed:
November 4, 2020
Date of Patent:
February 6, 2024
Assignee:
Progressive Sterilization, LLC
Inventors:
Barry M. Snyder, Clarence J. Snyder, III, Michele Mauzerall, Maryellen Keenan
Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and disposed in strings. A control means is coupled to the word lines and the strings and is configured to ramp a voltage applied to a selected one of the word lines from a verify voltage to a reduced voltage during a program-verify portion of a program operation. The control means successively ramps voltages applied to each of a plurality of neighboring ones of the word lines from a read pass voltage to the reduced voltage beginning with ones of the plurality of neighboring ones of the word lines immediately adjacent the selected one of the word lines and progressing to ones of the plurality of neighboring others of the word lines disposed increasingly remotely from the selected one of the word lines during the program-verify portion of the program operation.
Abstract: Deep gate-all-around semiconductor devices having germanium or group 111-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure and has a composition different from the upper and lower layers of the hetero-structure. A gate electrode stack is disposed on and completely surrounds a channel region of the active layer, and is disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure. Source and drain regions are disposed in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack.
Type:
Grant
Filed:
February 12, 2021
Date of Patent:
February 6, 2024
Assignee:
Google LLC
Inventors:
Ravi Pillarisetty, Willy Rachmady, Van H. Le, Seung Hoon Sung, Jessica S. Kachian, Jack T. Kavalieros, Han Wui Then, Gilbert Dewey, Marko Radosavljevic, Benjamin Chu-Kung, Niloy Mukherjee
Abstract: Individual clock adjustments between electronic devices are typically based around a round-trip time (RTT) measurement of the reference message between initiating and the receiving devices. With increasing expectations of clock synchronization accuracy, as well as widespread use of wireless data networks, the presently disclosed technology provides a dedicated clock synchronization network that yields a fixed delay between hops and within associated devices of a dedicated clock synchronization network. By accounting for the known delays between hops and within associated devices of the dedicated clock synchronization network, better clock synchronization accuracy can be achieved than prior art techniques that estimate latency based on an RTT measurement.
Type:
Grant
Filed:
August 11, 2022
Date of Patent:
February 6, 2024
Assignee:
Microsoft Technology Licensing, LLC
Inventors:
Woo Suk Lee, Flavio Protasio Ribeiro, Alexander Popovich