Patents Assigned to LSI Corporation
  • DE-INTERLEAVING ON AN AS-NEEDED BASIS
    Publication number: 20150106577
    Abstract: One embodiment is an apparatus having a memory, a controller, and a de-interleaving module. The memory is configured to store portions of a set of interleaved values, where the set of interleaved values correspond to a single application of an interleaving mapping to a set of un-interleaved values. The controller is configured to retrieve each portion from an other memory that stores the set of interleaved values by moving the portion from the other memory to the memory. The de-interleaving module is configured to de-interleave the interleaved values in at least one of the portions to generate a de-interleaved portion such that processing downstream of the de-interleaving module can begin processing the de-interleaved portion before all of the interleaved values in the set of interleaved values are de-interleaved by the de-interleaving module.
    Type: Application
    Filed: October 14, 2013
    Publication date: April 16, 2015
    Applicant: LSI CORPORATION
    Inventors: Kannan Rajamani, Ramon Sanchez, Kevin R. Kinney
  • DIGITAL FREQUENCY BAND DETECTOR FOR CLOCK AND DATA RECOVERY
    Publication number: 20150103961
    Abstract: A frequency band estimator for use in a data receiver or the like to enhance sinusoidal jitter tolerance by the clock and data recovery device (CDR) in the receiver. The detector uses two moving-average filters of different tap lengths that receive a gain-controlled signal from within the CDR. Output signals from the moving average filters are processed to determine a half-wave time period for each output signal by measuring the number clock cycles occurring between transitions of each output signal. The number of clock cycles of the longest half-wave period is compared to multiple values representing frequency limits of various frequency bands to determine which frequency band to classify jitter the gain-controlled signal. The determined frequency band is used to select from a look-up table a set of gain values for use in the CDR.
    Type: Application
    Filed: October 14, 2013
    Publication date: April 16, 2015
    Applicant: LSI Corporation
    Inventors: Amaresh V. Malipatil, Shiva Prasad Kotagiri, Sundeep Venkatraman, Sunil Srinivasa, Pervez M. Aziz
  • Systems and Methods for Multi-Algorithm Concatenation Encoding and Decoding
    Publication number: 20150106675
    Abstract: Systems and method relating generally to data processing, and more particularly to systems and methods for encoding and decoding information.
    Type: Application
    Filed: November 5, 2013
    Publication date: April 16, 2015
    Applicant: LSI Corporation
    Inventors: Shu Li, Fan Zhang, Bruce A. Wilson, Jun Xiao
  • MEMORY ARRAY ARCHITECTURES HAVING MEMORY CELLS WITH SHARED WRITE ASSIST CIRCUITRY
    Publication number: 20150103604
    Abstract: A memory device includes a memory array having a plurality of memory cells each having first and second power supply nodes, first and second virtual power supply nodes, a latch circuit, and a write assist circuit. The latch circuit includes a first and second inverters in a cross-coupled inverter configuration. The first inverter is connected between the first virtual power supply node and the second power supply node, and the second inverter is connected between the second virtual power supply node and the second power supply node.
    Type: Application
    Filed: December 11, 2013
    Publication date: April 16, 2015
    Applicant: LSI Corporation
    Inventors: Mohammed S.K. Sheikh, Setti S. Rao, Vinod Rachamadugu
  • Speculative Bit Error Rate Calculator
    Publication number: 20150106666
    Abstract: An apparatus for calculating a speculative bit error rate includes a data decoder operable to iteratively decode received data to yield decoded data, and a speculative bit error calculator operable to calculate a bit error rate based on the decoded data and the received data while the data decoder is decoding the received data. The bit error rate is updated with each decoding iteration in the data decoder.
    Type: Application
    Filed: October 12, 2013
    Publication date: April 16, 2015
    Applicant: LSI Corporation
    Inventors: Alexander Hubris, Vidyuth Srivatsaa, Bing Ji
  • Methods and structure for reduced layout congestion in a serial attached SCSI expander
    Patent number: 9007943
    Abstract: Methods and structure for reduced layout congestion in a switching device integrated circuit. A switching device such as a Serial Attached SCSI (SAS) expander comprises a switching circuit to couple any of a plurality (“N”) of physical links of the switching device with any other physical link of the switching device. The switching circuit comprises a first stage circuit adapted to couple any of the N physical links with a selected one of N/2 communication paths of the switching circuit and comprises a second stage circuit adapted to couple any of the N/2 communication paths with any of the N physical links. Since only N/2 communication paths may be active at any time in such a switching device, a control unit of the switching device tracks which of the N/2 communication paths are presently in use or unused so that an unused path may be selected for a new connection.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: April 14, 2015
    Assignee: LSI Corporation
    Inventor: Tejas Tayade
  • Intelligent data buffering between interfaces
    Patent number: 9009370
    Abstract: A dynamically controllable buffering system includes a data buffer that is communicatively coupled between first and second data interfaces and operable to perform as an elasticity first-in-first-out buffer in a first mode and to perform as a store-and-forward buffer in a second mode. The system also includes a controller that is operable to detect data rates of the first and second data interfaces, to operate the data buffer in the first mode when the first data interface has a data transfer rate that is faster than a data transfer rate of the second data interface, and to operate the data buffer in the second mode when the second data interface has a data transfer rate that is faster than the data transfer rate of the first data interface.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: April 14, 2015
    Assignee: LSI Corporation
    Inventors: Richard Solomon, Eugene Saghi, John C. Udell
  • Adjustment of data storage capacity provided by a storage system
    Patent number: 9009440
    Abstract: A storage system stores data in at least one partition of a physical storage media in accordance with file system information specifying a plurality of logical blocks having logical block addresses within the partition. The logical blocks include excess logical blocks that are not mapped to space in the physical storage media by the mapping employed by the storage system. Unusable block data marks those excess logical blocks as unusable. This makes it easy to adjust the data storage capacity of the storage system by changing the mapping to map more or less logical block addresses to space in the physical storage media and thereby destroy or create excess logical blocks, and by changing the unusable block data to correspondingly change the excess logical blocks marked as unusable.
    Type: Grant
    Filed: November 12, 2007
    Date of Patent: April 14, 2015
    Assignee: LSI Corporation
    Inventors: Duncan Beadnell, Don Harwood
  • Systems and methods for reusing a layered decoder to yield a non-layered result
    Patent number: 9009557
    Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data decoding.
    Type: Grant
    Filed: January 21, 2013
    Date of Patent: April 14, 2015
    Assignee: LSI Corporation
    Inventors: Shu Li, Zongwang Li, Shaohua Yang, Fan Zhang, Chung-Li Wang
  • Sharing of bypassed I/O transaction information
    Patent number: 9009375
    Abstract: A first I/O transaction request is sent to a storage controller for processing by firmware running on the storage controller. A second I/O transaction request is sent to storage hardware without further processing by the firmware running on the storage controller. Since the firmware did not process the second I/O transaction request, information associated with the second I/O transaction is stored in in a circular buffer accessible to the firmware running on the storage controller. The firmware running on the storage controller reads, from the circular buffer, the information associated with the second I/O transaction that was stored in the circular buffer.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: April 14, 2015
    Assignee: LSI Corporation
    Inventors: Gerald E. Smith, James A. Rizzo, Robert L. Sheffield, Anant Baderdinni
  • Methods and systems for instantaneous online capacity expansion
    Patent number: 9009405
    Abstract: The disclosure provides instantaneous, vertical online capacity expansion (OCE) for redundant (e.g., RAID-5, RAID-6) and non-redundant (e.g., RAID-0) arrays. The new OCE technique implements vertical expansion instead of the horizontal expansion techniques implemented in current OCE techniques. The vertical expansion treats any new addition of storage as an extension of the capacity of the preexisting physical drives in order to avoid having to rewrite the data blocks of the original, preexisting storage devices. Vertical RAID expansion is implemented by installing one or more new physical storage devices in a device or partition configuration that corresponds to the physical configuration of the preexisting volume and loading new metadata received through the user interface into the firmware of the RAID controller to define the configuration of the expanded volume.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: April 14, 2015
    Assignee: LSI Corporation
    Inventor: Kapil Sundrani
  • Methods and apparatus for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding
    Patent number: 9007828
    Abstract: Methods and apparatus are provided for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding. A single sector can be stored across a plurality of pages in the flash memory device. Per-page control is provided of the number of sectors in each page, as well as the code and/or code rate used for encoding and decoding a given page, and the decoder or decoding algorithm used for decoding a given page. Multi-page and wordline level access schemes are also provided.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: April 14, 2015
    Assignee: LSI Corporation
    Inventors: Harley F. Burger, Erich F. Haratsch, Milos Ivkovic, Victor Krachkovsky, Andrei Vityaev, Clifton Williamson, Johnson Yen
  • ADAPTIVE POWER-DOWN OF DISK DRIVES BASED ON PREDICTED IDLE TIME
    Publication number: 20150100810
    Abstract: Systems and methods presented herein provide a storage system that adaptively powers-down one or more disk drives based on the predicted idle time of each disk drive. One embodiment includes a storage controller that includes a processor operable to track idle durations of the disk drive. When an idle duration ends, the processor associates the idle duration with a time window that includes that idle duration. Each time window is associated with a number of previous idle durations of the disk drive. Upon detection of a current idle duration, the processor identifies a time window with the highest number of previous idle durations of the disk drive. Then, the processor determines whether a maximum time associated with the identified time window exceeds a predetermined threshold. When the maximum time exceeds the predetermined threshold, the processor powers-down the disk drive.
    Type: Application
    Filed: February 5, 2014
    Publication date: April 9, 2015
    Applicant: LSI CORPORATION
    Inventors: Dipu Sreekumaran, Arun Chandrashekhar
  • VOLTAGE FOLLOWER HAVING A FEED-FORWARD DEVICE
    Publication number: 20150097611
    Abstract: A circuit is described that includes a voltage follower device and a feed-forward device. In an implementation, the circuit includes a voltage follower device that includes an input and an output. The voltage follower device is configured to transfer a voltage signal at least substantially unchanged from the input to the output of the voltage follower device. The circuit also includes a feed-forward device that includes an input and an output. The input of the feed-forward device is connected to the input of the voltage follower device and the output of the feed-forward device is connected to the output of the voltage follower device. The feed-forward device is configured to output the voltage signal to the output of the voltage follower device.
    Type: Application
    Filed: October 3, 2013
    Publication date: April 9, 2015
    Applicant: LSI Corporation
    Inventor: Ryutaro Saito
  • Multiple sync mark storage system
    Patent number: 9001445
    Abstract: A data processing system includes a number of analog to digital converters operable to sample analog signals obtained from a magnetic storage medium to yield digital signals, multiple sync mark detectors operable to search for a number of different sync marks in the digital signals, and a sync mark detector output comparator operable to compare an output of each of the sync mark detectors to identify detection errors.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: April 7, 2015
    Assignee: LSI Corporation
    Inventors: Rui Cao, Haitao Xia, Lu Lu
  • Encoder and decoder generation by state-splitting of directed graph
    Patent number: 9003263
    Abstract: A method of generating a hardware encoder includes generating a first directed graph characterizing a constraint set for a constrained system, identifying a scaling factor for an approximate eigenvector for the first directed graph, applying the scaling factor to the approximate eigenvector for the first directed graph to yield a scaled approximate eigenvector, partitioning arcs between each pair of states in the first directed graph, performing a state splitting operation on the first directed graph according to the partitioning of the arcs to yield a second directed graph, and generating the hardware encoder based on the second directed graph.
    Type: Grant
    Filed: January 15, 2013
    Date of Patent: April 7, 2015
    Assignee: LSI Corporation
    Inventors: Razmik Karabed, Shaohua Yang, Wu Chang, Victor Krachkovsky
  • System and method for power saving modes in multi-sensor magnetic recording
    Patent number: 9001446
    Abstract: A system and method for power management in a hard disk drive (HDD) assembly incorporating two or more read sensors includes directing a read/write head to follow a track; depowering one or more read sensors and readpath circuits associated with the read sensors; reading an analog readback signal through the first read sensor; processing the signal through an analog front-end to generate an input signal; sampling the input signal through an analog to digital converter at a first frequency to generate a first sampling signal; sampling the input signal through a second analog to digital converter at a second frequency to generate a second sampling signal; and generating a digital output signal from either or both sampling signals at a third sampling frequency through a digital signal processor. The method may additionally comprise adjusting a sampling frequency when power level reaches a threshold.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: April 7, 2015
    Assignee: LSI Corporation
    Inventors: Bruce A. Wilson, Richard Rauschmayer, Peter J. Windler, Jefferson E. Singleton, Shaohua Yang, Jeffrey P. Grundvig
  • FLASH MEMORY REFERENCE VOLTAGE DETECTION WITH TRACKING OF CROSS-POINTS OF CELL VOLTAGE DISTRIBUTIONS USING HISTOGRAMS
    Publication number: 20150092489
    Abstract: Cross-points of flash memory cell voltage distributions are determined by reading data from a portion of the flash memory two or more times using two or more different candidate reference voltages and determining corresponding decision patterns. The frequency of occurrence of the decision patterns in the data read from the flash memory is used to conceptually construct a histogram. The histogram is used to estimate the cross-points. Employing decision patterns enables multiple cross-point voltages to be determined with a minimum of read operations.
    Type: Application
    Filed: October 21, 2013
    Publication date: April 2, 2015
    Applicant: LSI Corporation
    Inventors: Yunxiang Wu, Abdel-Hakim Alhussien, Zhengang Chen, Sundararajan Sankaranarayanan, Erich F. Haratsch
  • REDUCING CURRENT VARIATION WHEN SWITCHING CLOCKS
    Publication number: 20150091620
    Abstract: An apparatus includes a glitchless divider and a glitchless multiplexer. The glitchless divider may be configured to generate a first system clock in response to a divider value and a clock signal received from a first source. The divider value changes from a first value to a second value in a predetermined number of steps. The glitchless multiplexer may be configured to select between said first system clock and a second system clock in response to a control signal.
    Type: Application
    Filed: October 3, 2013
    Publication date: April 2, 2015
    Applicant: LSI Corporation
    Inventor: Steven J. Pollock
  • Non-Binary Layered Low Density Parity Check Decoder
    Publication number: 20150092290
    Abstract: A non-binary layered low density parity check decoder includes a variable node processor operable to generate variable node to check node messages and to calculate perceived values based on normalized check node to variable node messages and on normalized decoder inputs, and to output normalized decoded values, and a check node processor operable to generate the check node to variable node messages based on normalized variable node to check node messages.
    Type: Application
    Filed: November 3, 2013
    Publication date: April 2, 2015
    Applicant: LSI Corporation
    Inventors: Dan Liu, Qi Zuo, Chung-Li Wang, Zongwang Li, Lei Wang