Abstract: Systems and method relating generally to data processing, and more particularly to systems and methods for combining recovered portions of a data set.

Abstract: An apparatus includes a non-volatile memory and a controller. The controller may be configured to track one or more channel parameters of the non-volatile memory. The controller may be further configured to estimate an erase state voltage distribution of the non-volatile memory by selecting one or more parameters of the erase state distribution from a look-up table based upon at least one of the one or more channel parameters.

Abstract: An apparatus comprising a memory and a controller. The memory may be configured to process a plurality of read/write operations. The memory may comprise a plurality of memory modules each having a size less than a total size of the memory. The controller may be configured to write user data using a redundancy scheme. Information about the redundancy is (i) stored in a location separate from the data and (ii) used to recover potentially corrupted user data.

Abstract: A method for encoding a reduced polar code is disclosed. The method generally includes steps (A) to (C). Step (A) may generate the intermediate codeword by polar code encoding input data. Step (B) may remove one or more bits from one of (i) a first part of the intermediate codeword and (ii) a second part of the intermediate codeword. Step (C) may generate an output codeword by concatenating the first part of the intermediate codeword with the second part of the intermediate codeword after the bits are removed.

Abstract: Methods and structure for task management in storage controllers of a clustered storage system. An initiator storage controller of the clustered storage system ships I/O requests for processing to a target storage controller of the system. Responsive to a need to abort a previously shipped I/O request, the initiator storage controller transmits a task management message to the target storage controller. The task management message identifies one or more previously shipped I/O requests to be aborted. The target storage controller processes the received task management message in due course of processing requests and completes processing for the aborted previously shipped request in an orderly manner. Resources associated with the aborted previously shipped requests are release within both controllers.

Abstract: Multi-layer in integrated transmission line circuits are provided having improved signal loss characteristics. A multi-layer integrated transmission line circuit, such as a stripline circuit or a microstrip circuit, comprises at least one reference layer; at least one conducting layer having one or more conducting strips, wherein the at least one conducting layer is separated from the at least one reference layer by a substrate; and at least one additional layer positioned between the at least one conducting layer and the at least one reference layer. The multi-layer integrated transmission line circuit may also comprise a dielectric insulating material, such as an organic material or a ceramic material. The additional layers increase a dielectric thickness of the multi-layer integrated transmission line circuit to reduce dielectric losses.

Abstract: A method and system for managing a cache for a host machine is disclosed. The method includes: indicating each cache line in the cache as being in a transitional meta-state when any virtual machine hosted on the host machine moves out of the host machine; each time a particular cache line is accessed, indicating that particular cache line as no longer in the transitional meta-state; and marking the cache lines still in the transitional meta-state as invalid when a virtual machine moves back to the host machine.

Abstract: Block-based crest factor reduction (CFR) techniques are provided. An exemplary block-based crest factor reduction method comprises obtaining a block of data samples comprised of a plurality of samples; applying the block of data to a crest factor reduction block; and providing a processed block of data from the crest factor reduction block. The block-based crest factor reduction method can optionally be iteratively performed a plurality of times for the block of data. The block of data samples can comprise an expanded block having at least one cursor block. For example, at least two pre-cursor blocks and one post-cursor block can be employed. The peaks can be cancelled, for example, only in the block of data samples and in a first of the pre-cursor blocks.

Abstract: Described embodiments provide a non-uniformly quantized analog-to-digital converter (ADC) for generating a value for each sample of a received signal. The ADC includes arrays of decision comparators provided the received signal. Each comparator has a threshold voltage set according to a corresponding bit history of a predictive decision feedback equalizer (DFE), and each bit history is associated with a tap of the DFE. Each comparator provides a bit value based on the corresponding bit history. The predictive DFE includes a set of interleave groups, each interleave group having j interleaves. Each interleave determines a bit value of a corresponding sample in a window of samples. Each tap corresponds to a feedback path between adjacent interleave groups. Multiplexing logic of each interleave predictively selects a bit value of an associated tap based on a value of a corresponding select line in a previous interleave, thereby alleviating a unit interval timing constraint.

Abstract: A method and apparatus are provided for access point selection in wireless communication systems, such as wireless LANs. A disclosed wireless communication device includes a roaming process that selects an access point based on a measure of correlation on a channel to one or more surrounding access points. The roaming process selects an access point, for example, having the lowest correlation value. The roaming process may also consider the signal quality, channel delay spread or both in selecting an access point.

Abstract: An apparatus includes a memory and a controller. The memory may be configured to implement a cache and store meta-data. The cache generally comprises one or more cache windows. Each of the one or more cache windows comprises a plurality of cache-lines configured to store information. Each of the plurality of cache-lines is associated with meta-data indicating one or more of a dirty state, an invalid state, and a partially dirty state. The controller is connected to the memory and may be configured to (i) detect an input/output (I/O) operation directed to a file system recovery log area, (ii) mark a corresponding I/O using a predefined hint value, and (iii) pass the corresponding I/O along with the predefined hint value to a caching layer.

Abstract: A magnetic recording system includes an array of analog inputs operable to receive an array of analog signals retrieved from a magnetic storage medium, where one of the array of analog signals corresponds with a reference channel, a timing recovery circuit operable to generate a clock signal based on the analog signal for the reference channel, a number of analog to digital converters each operable to sample one of the array of analog signals based on the clock signal to yield a number of digital channels, and a joint equalizer operable to filter the digital channels to yield an equalized output.

Abstract: A solid state drive and a method for providing active recycling for the solid state drive are disclosed. The solid state drive includes a plurality of blocks and each of the plurality of blocks includes a plurality of pages. The method steps include receiving a read request from a data requester; identifying at least one page containing data requested by the read request; determining whether the at least one page belongs to a block identified for active recycling; writing the at least one page to a different block when the at least one page belongs to the block identified for active recycling; and sending the at least one page to the data requester in response to the read request.

Abstract: Described embodiments provide a solid-state drive (SSD) including a media controller and a solid-state media. A control processor of the media controller determines a logical address, a transfer size, and map data based on the logical address and transfer size, associated with a read request received from a host device. Based on the logical address and a sequential zone defined based on one or more previous read requests, the control processor determines whether the received read request is a sequential read. A map data pre-fetch size is adjusted based on the transfer size of the received read request and whether the received read request is a sequential read. A corresponding portion of the map data is transferred from the solid-state media to a map cache coupled to the control processor, the transferred portion having a size equal to the adjusted map data pre-fetch size.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for variable rate encoding and/or decoding in a data processing system. In some cases, embodiments include a variable length data decoder circuit that is operable to apply a decode algorithm to the encoded input based upon a first selected H-Matrix to yield a first decoded output and apply the decode algorithm to the encoded input based upon a second selected H-Matrix to yield a second decoded output.

Abstract: A method for finding a valid codeword based on a near codeword trapping in a low-density parity-check decoding process includes identifying trapping set configurations and applying corrections to produce trapping sets with a limited number of invalid checks. Trapping set configurations are corrected in order to produce a trapping set in a table of trapping sets, the table associating each corrected trapping set with a valid codeword.

Abstract: An amplification system and an integrated circuit include a bandpass filter and an amplifier. The bandpass filter filters an input digital bitstream or an amplified signal to provide a filtered signal. The bandpass filter exhibits constant input impedance over a passband associated with the input digital bitstream, and a stopband associated with shaped-noise energy, thereby increasing signal-to-noise ratio and/or signal-to-distortion ratio associated with the filtered signal. The amplifier amplifies at least one of the filtered signal and the input digital bitstream to provide the amplified signal. A method of providing amplification includes bandpass filtering an input digital bitstream or an amplified signal to provide a filtered signal, providing constant input impedance over a passband and a stopband by the bandpass filtering, and amplifying at least one of the filtered signal and the input digital bitstream to provide the amplified signal.

Abstract: A layered LDPC decoder architecture includes a single MUX and a single shifter element for processing an optimized LDPC parity check matrix. The optimized LDPC parity check matrix may be a K×L sub-matrix having zero elements, non-zero elements defined by a circulant matrix or zero matrices, and identity matrixes.

Abstract: Systems and method relating generally to data processing, and more particularly to systems and methods for segmenting a data set and recovering the segmented data set. In one case, a system is disclosed that includes: a data transfer preparation circuit, a transfer characteristic determination circuit, and a a format insertion circuit. The data transfer preparation circuit is operable to receive a user data set and to generate an output data set based upon the user data set; the transfer characteristic determination circuit is operable to determine a distance between a first servo data wedge on a storage medium and a second servo data wedge on the storage medium; and the format insertion circuit is operable to dynamically augment the output data set with formatting information at a location selected based at least in part on the distance between the first servo data wedge and the second servo data wedge.

Abstract: A RAID data storage system incorporates permanently empty blocks into each stripe, distributed among all the data storage devices, to accelerate rebuild time by reducing the number of blocks that need to be rebuilt in the event of a failure.