Abstract: A random number generator includes a ring oscillator having an EX-OR gate and four inverters together forming a loop. This loop enters stable state for a start signal having the low level and oscillates for the start signal having the high level. When the start signal has a pulse of a width shorter than the loop's delay time, output nodes responsively, sequentially enter metastable state hovering between the high and low levels. The metastable waveform becomes smaller with time and finally disappears. As metastable state cannot be controlled in longevity, it disappears at any random number node. A counter thus outputs a signal serving as true random number data depending on the longevity of the metastable state. A random number generator miniaturized and having reduced power consumption, and of high performance can thus be implemented.

Abstract: The detector includes a plug for connecting a personal computer through a cable, a battery power supply which provides a constant power supply, and an MCU which receives a specific potential from the personal computer when the latter is connected.

Abstract: In a spread spectrum clock generator, a DLL circuit delays an oscillation clock signal from a VCO and outputs ten delay clock signals having different phases respectively. A selector selects any one of the ten delay clock signals, and outputs a selected clock signal. A control circuit controls a signal selection operation of the selector. A feedback frequency divider divides a frequency of the selected clock signal by a frequency division ratio N, and generates a comparison clock signal. In this manner, a phase of the comparison clock signal can be fine-tuned. Therefore, a spread spectrum clock generator capable of frequency modulation with high accuracy can be obtained.

Abstract: A random number generator includes a ring oscillator having an EX-OR gate and four inverters together forming a loop. This loop enters stable state for a start signal having the low level and oscillates for the start signal having the high level. When the start signal has a pulse of a width shorter than the loop's delay time, output nodes responsively, sequentially enter metastable state hovering between the high and low levels. The metastable waveform becomes smaller with time and finally disappears. As metastable state cannot be controlled in longevity, it disappears at any random number node. A counter thus outputs a signal serving as true random number data depending on the longevity of the metastable state. A random number generator miniaturized and having reduced power consumption, and of high performance can thus be implemented.

Abstract: A random number generator includes a ring oscillator having an EX-OR gate and four inverters together forming a loop. This loop enters stable state for a start signal having the low level and oscillates for the start signal having the high level. When the start signal has a pulse of a width shorter than the loop's delay time, output nodes responsively, sequentially enter metastable state hovering between the high and low levels. The metastable waveform becomes smaller with time and finally disappears. As metastable state cannot be controlled in longevity, it disappears at any random number node. A counter thus outputs a signal serving as true random number data depending on the longevity of the metastable state. A random number generator miniaturized and having reduced power consumption, and of high performance can thus be implemented.

Abstract: The detector includes the plug for connecting the personal computer through a cable, battery power supply which provides a constant power supply, and the MCU which receives a specific potential from the personal computer when the later is connected.

Abstract: A replacement cell determining part is configured so as not to handle, as a cell that should be replaced, the case where the sole difference is the cell identification name and other data are matched, in addition to the case where all of the cell identification name, the cell type name, the pin name of the cell, and the signal name assigned to the pin are matched. A rerouting signal determining part is configured so as not to handle, as a signal that should be rerouted, the case where the sole difference is the signal name and other data are matched, in addition to the case where all of the signal name, the pin name to which the signal is applied, the cell identification name of a cell possessed by the pin, and the cell type name of the cell are matched.

Abstract: A data/clock recovery circuit can recover high-rate data using the data as a clock signal. It includes an edge detector, a clock selection signal generating circuit, a clock selection circuit and a synchronizing circuit. The edge detector generates edge position information using a receiver output as a clock signal. The clock selection signal generating circuit generates a clock selection signal in response to the edge position information using the receiver output as the clock signal. The clock selection circuit selects a recovered clock signal from a clock signal group in response to the clock selection signal. The synchronizing circuit synchronizes the receiver output using the recovered clock signal, and outputs it as a synchronized data signal.

Abstract: A teletext data separation apparatus has a slice level generating circuit including a slice timing control circuit, a control register, an adder and a divider. The slice timing control circuit generates a timing signal for sampling. The control register carries out ON/OFF control of the slice timing control circuit. The control register sets by its register value the number of the sampling points of the adder and divider. By varying the register value in response to the reception state, the number of the sampling points can be increased from the specified 16 points, for example. This makes it possible for teletext data separation apparatus to generate an appropriate slice level that enables the teletext data to be separated reliably even in conditions where noise or distortion occurs in the video signal because of the effect of a weak electric field or ghost.

Abstract: An A/D converter updates its reference potential so that it coincides with an analog potential of a video signal. The A/D converter changes a variable voltage range of the reference potential during the same horizontal synchronizing period based upon a horizontal synchronizing signal. It is possible to correctly discriminate data superposed on the video signal even if an analog potential of the video signal considerably varies during the same horizontal synchronizing period.

Abstract: A fault simulator includes a circuit identifying section that selects, as fault generation points, circuit components subjected to a simulation from timing simulation results obtained by a static timing simulation of an LSI circuit; a fault value computing section that generates delay faults corresponding to the fault generation points using information about delay time and timing of signal transmission in the timing simulation result; and a fault simulating section that performs, by using a test pattern of the simulation, a logic simulation of a normal circuit of the LSI circuit and that of a faulty circuit where the delay faults are inserted into the fault generation points, and verifies detectability of the delay faults by the test pattern from the compared results of both the logic simulations. The fault simulator can reduce the time of the fault simulation.

Abstract: The detector includes the plug for connecting the personal computer through a cable, battery power supply which provides a constant power supply, and the MCU which receives a specific potential from the personal computer when the later is connected.

Abstract: A power-residue calculating circuit includes: an I/F (interface) circuit with respect to an external bus; an e register holding a key e; a Y register holding a multiplier Y for Montgomery conversion; an N register holding a key N; a B2N register holding a value of (2B+N) calculated during the Montgomery conversion; an X register holding a plaintext X; a calculating circuit performing calculations for encryption and decryption; a P register holding a calculation result P; a power-residue control circuit serving as a state machine when the power-residue calculation is performed; a Montgomery multiplication residue/residue control circuit serving as a state machine when the Montgomery multiplication residue calculation and residue calculation are performed; and an addition/subtraction control circuit controlling calculations addition and subtraction.

Abstract: A semiconductor integrated circuit is capable of filling the need for more memory space through the effective use of an already-designed core block. A block (1) including a CPU, an array (4a) of a plurality of bonding pads, and RAMs (21a, 22a) which are first memories located on the same side of the array (4a) as the block (1) are already designed. The requirement for increased memory capacity can be filled with ease by the addition of RAMs (24a, 25a) which are second memories located on the opposite side of the array (4a) from the block (1). Since the second memories are different in physical configuration from the first memories, it is easy to design a physical configuration to achieve required memory capacity outside a core block (8a) within a single-chip microcomputer (9c).

Abstract: The number of pulses of a clock signal CLK-A is circularly counted in a count range from “0” to “7”, and count signals indicating count values are produced. A clock signal CLK-B having a frequency lower than that of the clock signal CLK-A is produced from count signals of “3” and “7”, and data transfer between a high speed operating block operated in synchronization with the clock signal CLK-A and a low speed operating block operated in synchronization with the clock signal CLK-B is performed in synchronization with the clock signal CLK-B to receive input serial data or transmit output serial data. When a stuff bit of universal Serial Bus is detected in the input serial data or is inserted in the output serial data, a cycle of the clock signal CLK-B is lengthened by one cycle of the clock signal CLK-A.

Abstract: A free page extracting unit extracts a free page of a non-volatile memory. A directory page writing unit writes, to the free page extracted by the free page extracting unit, a directory that includes a logical page/physical page translation table of a page to which updated data are to be written. Further, a data page writing unit writes updated data to the free page extracted by the free page extracting unit. Therefore, even when data updating operation is interrupted, loss of the original data can be prevented, and the data before updating can be recovered.

Abstract: A screen display unit includes a display RAM to which a CPU writes palette codes corresponding to character codes, and a selector for selecting display color data read from one of two color palettes on a character code by character code basis in response to the palette codes read from the display RAM. The selector can select one of the two color palettes on a character code by character code basis, thereby making it possible to carry out display in a greater number colors on the same screen than the number of colors indicatable by the display color codes stored in the display RAM without increasing the capacity of a font data memory.

Abstract: An input circuit of a one-chip microcomputer is connected to an external switching circuit. When an analog input signal of a significant level generated in the external switching circuit is received at an analog input terminal of the input circuit, an A/D conversion start request signal is generated in an A/D conversion start request generating circuit and is sent to an A/D converter. The operation of the A/D converter is started in response to the A/D conversion start request signal, the analog input signal received at the analog input terminal is converted into digital data, and an A/D conversion finish signal is sent from the A/D converter to a CPU of the one-chip microcomputer. The operation of the CPU is started in response to the A/D conversion finish signal, and the digital data is readout to the CPU.

Abstract: A random number generator includes a ring oscillator having an EX-OR gate and four inverters together forming a loop. This loop enters stable state for a start signal having the low level and oscillates for the start signal having the high level. When the start signal has a pulse of a width shorter than the loop's delay time, output nodes responsively, sequentially enter metastable state hovering between the high and low levels. The metastable waveform becomes smaller with time and finally disappears. As metastable state cannot be controlled in longevity, it disappears at any random number node. A counter thus outputs a signal serving as true random number data depending on the longevity of the metastable state. A random number generator miniaturized and having reduced power consumption, and of high performance can thus be implemented.

Abstract: In a spread spectrum clock generator, a DLL circuit delays an oscillation clock signal from a VCO and outputs ten delay clock signals having different phases respectively. A selector selects any one of the ten delay clock signals, and outputs a selected clock signal. A control circuit controls a signal selection operation of the selector. A feedback frequency divider divides a frequency of the selected clock signal by a frequency division ratio N, and generates a comparison clock signal. In this manner, a phase of the comparison clock signal can be fine-tuned. Therefore, a spread spectrum clock generator capable of frequency modulation with high accuracy can be obtained.