Abstract: A data processor including an alternative clock generator for generating, in a power saving mode, an alternative clock signal which is supplied to a peripheral circuit instead of a system clock signal. This enables only the peripheral circuit such as an A/D converter to be put into operation in response to the alternative clock signal in the power saving mode. This solves a problem of a conventional data processor in that it cannot achieve the power saving efficiently because it is unavoidable for the remaining portion of the conventional data processor like a CPU to be involved in a high-rate operation along with the peripheral circuit even if it is desired to operate only the peripheral circuit at a high-rate when releasing the sleep mode or changing the sleep mode to a high-rate mode.

Abstract: A semiconductor device test board solves a problem with conventional test boards in that test results obtained through a burn-in procedure could be identified only before the test board is taken out of a burn-in oven. Hence, conventional test boards required additional steps for checking the test results after removing the test boards from the burn-in oven. This extra step prevents the efficiency of the test from being improved. One embodiment of the present test board has indicator arms, each rotatably mounted on a pivot on the test board, for indicating, in response to a signal on a signal line, the test result of the semiconductor device associated with it. Each of the indicator arms maintains its rest position when no failure has occurred in the semiconductor device associated with it during the test.

Abstract: A charge pump circuit comprises a plurality of booster stages. Each booster stage has a first node, a second node, a first charge pump and a second charge pump. Both charge pumps operate in a complementary manner, and raise potential of the second node relative to potential of the first node by transferring charge from the first node to the second node. Each charge pump comprises a pumping capacitor, an NMOS transistor and a PMOS transistor. In each charge pump, the NMOS transistor is used for charging the pumping capacitor with charge input through the first node, and the PMOS transistor is used for discharging the pumping capacitor to send charge to the second node.

Abstract: A field decision unit capable of solving a problem involved in a conventional field decision unit in that an internal synchronizing signal can be erroneously synchronized with the equalizing pulses of a video signal owing to noise because the output halt period of a phase comparator is set rather short considering that this will facilitate the synchronization of the internal synchronizing signal with the video signal when starting the system or the like, and hence an incorrect field decision can be made. The present field decision unit includes an output controller which sets output halt pulses with a longer output halt period in a particular interval consisting of the synchronizing cycles containing the equalizing pulses and a synchronizing cycle previous thereto, and which employs output halt pulses with a shorter output halt period outside the particular interval as in the conventional system.

Abstract: A test circuit includes a writing unit that outputs m-bit data captured upon receipt of a clock signal, branches the m-bit data n identical m-bit data signals, and stores the n m-bit data signals in a memory device. A function determining unit reads the n m-bit data signals from the memory, compares one of the n m-bit data signals to an m-bit expected value, and determines coincidence or non-coincidence between the n m-bit data signal and an expected value.

Abstract: An operation mode transfer system capable of solving a problem of a conventional system in that a processing load of a host computer cannot be reduced as long as a device is physically connected with the host computer because the host computer must carry out, even when the device is inoperative, the same communication processing as that performed when the device is operative. The present system connects a pullup resistor to a pullup power supply to set the device operative, and disconnects it from the pullup power supply to set the device inoperative, in response to the instructions from a CPU of the device.

Abstract: A microcomputer contains an electrically erasable flash memory for storing a program under development and a debugging circuit 7 having a dedicated input/output terminal for connection to an external ICE 14, and the debugging circuit 7 has a function of communication with a CPU 1, a function of communication with the ICE 14, a function of tracing the operating condition of the CPU 1, a break function of generating a debug interrupt, a function of writing a program code from the ICE 14 into the flash memory 6 and a function of sending the contents of the flash memory 6 to the ICE 14.

Abstract: A logical simulation device has a delay value calculations section to calculate delay values of circuit blocks in a semiconductor integrated circuit as a target of logical simulation based on logical circuit information relating to the logical circuit blocks, input test patterns as operational descriptions of used in circuit verification, and delay value calculation information stored in a delay value and timing check value calculation library, and a logical simulation section performs the logical simulation of the semiconductor integrated circuit based on the calculated delay values.

Abstract: A non-contact type IC card includes a rectifier circuit for supplying a source voltage to respective circuits of an IC card based on the strength of radio waves received from a host computer. A reference voltage generating circuit generates a reference voltage. A comparison circuit compares the source voltage with the reference voltage. A control circuit prohibits the writing of data if the source voltage becomes less than the reference voltage.

Abstract: A semiconductor device capable of solving a problem of a conventional semiconductor device in that a high density integration cannot be expected because each cell, which includes a pair of N and P wells disposed adjacently, requires a countermeasure against latchup individually. The high density integration prevents an effective countermeasure against latchup. The present semiconductor device arranges two cells, which are adjacent in the direction of an alignment of the N wells and P wells, in opposite directions so that two P wells (or two N wells) of the two adjacent cells are disposed successively, and includes an isolation layer extending across the two adjacent cells to enclose the two successively disposed P wells, thereby isolating the two P wells collectively from the substrate.

Abstract: A semiconductor integrated circuit includes a fuse element located on an insulating layer. The surface of the insulating layer is substantially smooth. The insulating layer is located over a capacitor. Wiring is located on the insulation layer. The fuse element and the wiring include the same material.

Abstract: A semiconductor memory device is constituted such that, when a first wiring layer provides a bit line of a first common complementary data line pair and a third wiring layer provides a bit line of a second common complementary data line pair, a second wiring layer makes an overlapped area between the bit line and the bit bar line of the second common complementary dada line pair equal to the bit line of the first common complementary data line pair and also an overlapped area between the bit line and the bit bar line of the first common complementary data line pair equal to the bit line of the second common complementary data line pair.

Abstract: An on-screen display unit solves a problem of a conventional on-screen display unit. The conventional unit cannot implement a moving display of an image with a small amount hardware. The novel on-screen display unit includes a first memory for storing the image code of each of images to be displayed. A second memory stores font data of the images. A latch circuit stores information indicating one of a moving display ON mode and a moving display OFF mode. A line memory stores at least one horizontal line image. An image data generating unit generates image data to be stored in the line memory. A selector selects output data from the second memory when the latch circuit stores information indicating the moving display OFF mode and selects output data from the line memory when the latch circuit stores information indicating the moving display ON mode.

Abstract: Oscillating circuitry built in integrated circuitry (1) comprises a ring oscillator (31) for generating a first clock, an external oscillator (40) capable of generating a second clock in either one of two oscillating modes which is determined according to an external circuit (12 and 13, or 6 through 8) connected to terminals (2 and 3) thereof, and an internal clock selection circuit (41) which delivers the first clock as an internal clock to the integrated circuitry (1) just after the integrated circuitry (1) is activated or reset, stops the delivery of the first clock and simultaneously furnishes a signal held at a logic high level as the internal clock in response to a control signal for instructing a selection of the second clock, and then determines whether or not the external oscillator (40) is generating the second clock properly, and which furnishes the second clock as the internal clock when it determines that the external oscillator (40) is generating the second clock properly.

Abstract: A semiconductor memory device includes memory elements, each maintaining memory contents within a period of time during which a refresh operation is repeated, and a refresh request circuit for making a refresh request. The semiconductor memory device includes refreshing circuits each of which, in response to a refresh request from the refresh request circuit, performs a refresh operation on a different number of memory elements at the same time, and a selecting circuit for selecting one refreshing circuit from among the refreshing circuits according to the number of memory elements included in the semiconductor memory device. The refresh request circuit can change the interval at which it makes a refresh request.

Abstract: A pattern data generating system solves a problem of a conventional pattern data generating system in which the total processing time is prolonged. The present pattern data generating system includes a parallel processing number calculator for computing the number of parallel processes to be used by a region divider that sequentially distributes the split pattern data. A group of pattern data generators generate pattern data in parallel processes. A pattern data combiner combines the pattern data output from the pattern data generators. A parallel processing controller controls the processing.