Abstract: Systems and methods herein provide for load balancing Fibre Channel traffic. In this regard, a Fibre Channel load balancer may be operable to monitor Fibre Channel paths coupled to a host bus adapter and determine the speeds of the Fibre Channel ports within the Fibre Channel paths. The Fiber Channel load balancer may also be operable to determine certain characteristics of the Fibre Channel traffic being passed over the Fibre Channel paths. For example, a load balancer may determine Fibre Channel traffic sizes of pending requests and, based in part on the traffic sizes and operable normalized speeds of the Fibre Channel ports, adaptively route the pending original traffic across the Fibre Channel ports.

Abstract: A method of planarizing a first side of a semiconductor wafer with a polishing system includes the step of polishing the first side of the wafer in order to remove material from the wafer. The method also includes the step of moving a lens of a confocal optical system between a number of lens positions so as to maintain focus on the first side of the wafer during the polishing step. The method further includes the step of determining a rate-of-movement value based on movement of the lens during the moving step. Moreover, the method includes the step of stopping the polishing step if the rate-of-movement value has a predetermined relationship with a movement threshold value. An apparatus for polishing a first side of a semiconductor wafer is also disclosed.

Abstract: An optical disk controller reads CD-ROM disks at high speeds that commonly produce errors. Errors in the headers that identify sectors are tolerated by the sector-search hardware. The disk-controller firmware writes a virtual target register the previous sector's header's minutes, seconds, frame (MSF), which is one less that the desired sector's MSF, or MSF-1. A physical target that precedes the virtual target is searched for. The physical target precedes the desired sector by N sectors, so that the physical target is MSF-N. When the physical target matches a header read from the disk, a good sector found flag is set. The physical target is then incremented for each new sector and compared to the virtual target. Once the physical target matches the virtual target, the following sector is buffered to the host. The raw header from the disk is stored and error corrections are made using the error correction byte following the sector's data.

Abstract: A demodulator for digital-versatile disk (DVD) optical disks converts 16-bit codewords stored on the disk into 8-bit symbols or user bytes that are sent to the host after error correction. Rather than use the modulation tables in the DVD specification in reverse, the entries in the modulation table are sorted and combined. The four states stored in the DVD modulation table are reduced to two states or conditions. All entries from states 1 and 4 are sorted into unique tables that have unique mappings of codewords to symbols. Since the unique mappings are not sequence or state dependent, no state information is stored in the unique tables. Entries from states 2 and 3 are sorted into duplicates tables that have duplicate mappings, where a codeword can map to two different symbols, depending on the state sequence. One of the two symbols is chosen based on bits in the following codeword, which is the next state.

Abstract: One or two, or more, additional conductive layers, separated from one another (if two or more) and separated from a patterned (signal) conductive layer are formed in a flexible substrate, for mounting a semiconductor die in a semiconductor device assembly. These additional layers are used as separate planes for carrying power and/or ground from outside the assembly to the die, on a separate plane from signals entering or exiting the die. TAB processes are disclosed for cutting, bending and bonding inner and outer portions of selected signal layer traces to respective inner and outer edge portions of the additional conductive layer(s), including a two-stage process of (1) first cutting, bending and tacking the selected traces to the additional layer(s), and then (2) repositioning a bonding tool and securely bonding the selected traces to the additional layer(s). A tool (die pedestal) for aiding in the assembly process is also disclosed.

Abstract: A system for globally prioritizing and scheduling I/O requests from a plurality of storage users or clients to one or more storage objects. The system comprises a storage controller configured to receive I/O requests from the client workstations and prioritize and schedule those I/O requests in accordance with a scheduling algorithm. Specifically, the storage controller receives I/O requests from the storage users and places the I/O requests in memory queues associated with the particular storage users. The storage controller then selects the I/O requests from the various memory queues based on the scheduling algorithm.

Abstract: A subscriber station for decrypting and decompressing data is provided on a single chip. The chip includes a DES decryption unit for performing decryption of incoming data with a DES key, a public key decryption unit for decrypting the DES key, a general purpose microprocessor for performing decompression, and a Secure Buffer for protecting the decrypted data prior to decompression. The chip includes an embedded key for the public key decryption unit and a bus for providing a data communication path between the microprocessor and the decryption units.

Abstract: One aspect of the invention relates to a semiconductor substrate. In one version of the invention, a semiconductor substrate includes a package substrate having first and second surfaces with conductive traces formed thereon and structures for providing electrical connection between selected conductive traces, a die attach area on the first surface of the package substrate adapted to provide physical connection to a semiconductor die, the die attach area having conductive contacts for providing electrical connection between the die and conductive traces on the first surface, a package frame, at least one substrate strap which connects the package substrate to the package frame, the substrate strap being formed integrally with the package substrate and the package frame.

Abstract: A repeating cell structure in a semiconductor substrate for a BiCMOS logic gate array. The cell structure has three regions shaped as columns. The first columnar region is a P-well and has four vertically aligned active areas of N-type material formed within the columnar region. Each of the active areas has two gate electrodes to form two NMOS transistors. Similarly the second columnar region is a N-well and has four vertically aligned active areas of P-type material. Each such active region forms two PMOS transistors. The third column has two bipolar transistors, each with collector, base and emitter regions vertically aligned. The resulting BiCMOS logic array permits a flexible location of macrocells, which results in a compact implementation of the resulting integrated circuit.

Abstract: Methods and associated apparatus for performing concurrent I/O operations on a common shared subset of disk drives (LUNs) by a plurality of RAID controllers. The methods of the present invention are operable in all of a plurality of RAID controllers to coordinate concurrent access to a shared set of disk drives. In addition to providing redundancy features, the plurality of RAID controllers operable in accordance with the methods of the present invention enhance the performance of a RAID subsystem by better utilizing available processing power among the plurality of RAID controllers. Under the methods of the present invention, each of a plurality of RAID controllers may actively process different I/O requests on a common shared subset of disk drives. One of the plurality of controllers is designated as primary with respect to a particular shared subset of disk drives.

Abstract: A programmable substrate and a method of making a programmable substrate for use with array-type packages, including Ball Grid Arrays(BGA), Pin Grid Arrays (PGA) and Column Grid Arrays (CGA) includes a nonconductive programmable substrate with a cavity in the top of the substrate. The cavity is sized to receive an integrated circuit (IC) die. An array of electrically conductive vias pass through the substrate. A plurality of electrical traces are formed on the top of the substrate. The traces extend radially from an edge of the die cavity to the periphery of the substrate so as to pass between and near the vias. Each trace is electrically connected to a pad of the IC die by a wire bond. Each via is connected on a bottom surface of the substrate to a solder ball, pin, or other means for electrically and mechanically attaching the substrate to a printed circuit board. The traces are programmably connected to a selected via, e.g.

Abstract: A method of testing a semiconductor device includes generating a current waveform for the semiconductor device by measuring the response of the device to an initializing vector group and comparing the current waveform to a golden waveform to determine whether the semiconductor device is good or defective. Apparatus for testing the semiconductor device includes a vector generator providing an initialization vector group to the semiconductor device, a measurement unit for measuring a plurality of current measurements from the semiconductor device which responds to the input of the initialization vector group, a generation unit for generating a current waveform from the current measurements of the semiconductor device, and an analysis unit for comparing the current waveform to a golden waveform to determine whether the device falls outside a tolerance margin of the golden waveform.

Abstract: A random number generating apparatus for an interface unit of a Carrier Sense with Multiple Access and Collision Detect (CSMA/CD) Ethernet data network. The interface unit includes a transmit backoff unit for implementing a backoff algorithm in response to a network collision signal and a random number. The apparatus comprises a dual mode random number generator and a multiplexer for switching the random number generator between modes in accordance with the serial address bits of a data packet being processed by the interface unit. The random number generator includes a 25 stage linear feedback shift register. The multiplexer has two signal inputs connected to outputs of the 18th and 22nd stages of the shift register respectively, a switch input connected to receive the serial address bits and an output connected in circuit to an input of the shift register.

Abstract: A test method and means for in integrated circuit (10) having asynchronous communication capabilities including a transmitter (12) and a receiver (14). A pattern generator (24) is provided for generating patterns directly from within the integrated circuit (10). In the best presently known embodiment, a serializer (16) provides a serial output (20) and a deserializer (18) processes a serial input (22) into a parallel signal and provides the parallel signal to a receiver (14). The pattern generator (24) is preprogrammed to provide a parallel data pattern which can optionally and intermittently be provided to the transmitter (12) in a test mode (44). In the test mode (44), signal is routed from the serializer (16) directly to the deserializer (18) via an external loop back path (34) or an internal alternative loop back path (34a).

Abstract: According to the present invention, a method is provided for attaching a package substrate to a circuit board. In one version of the invention, the package substrate has a semiconductor die disposed thereon, and the semiconductor die has a plurality of bond pads formed thereon which are electrically connected to conductive traces on the package substrate. In one embodiment of the invention, the method comprises the steps of attaching a first surface of an electrical connector to one of the conductive traces by thermoplastic adhesion; and attaching a second surface of the electrical connector to a conducting pad on the circuit board, also by thermoplastic adhesion.

Abstract: A technique is described for testing the performance of a target electronic system ultimately employing an ASIC comprising a core cell and surrounding logic, using an inchoate (designed, but not yet fabricated) ASIC on an interim basis. In one embodiment, a Q-part, or qualification part, which is essentially a bond-out of the core cell, is used in conjunction with programmable logic devices configured to perform the function of the surrounding logic. The Q-part and programmable logic are interconnected on a pod, and plugged into an interim version of a target electronic system. In another embodiment, the Q-part is software-simulated and interconnected on the pod to programmable logic devices. The programmable logic devices may be programmed either on-pod or off-pod, and signals incident to the operation of the pod plugged into the interim electronic system can be monitored and controlled.

Abstract: A method of choosing non-scan I/O nodes to replace with scan I/O nodes so as to allow the greatest amount of proprietary information to be removed from an ASIC core netlist which is to be supplied to an ASIC customer, includes the steps of assigning weights to core gates based upon how competitively sensitive those gates are determined to be, assigning a value to each non-scan I/O node based upon the sum of weights of all gates to which the I/O node is connected, and replacing the non-scan I/O node having the greatest value with a scan node. Gates that are within the timing shell are assigned a weight of zero. I/O nodes that are performance critical are assigned a value of zero, and the weights of all gates connected to such performance-critical I/O's are also set to zero. The I/O node selection process is iterative, with the weight of a gate being set to zero when it is connected to more non-scan I/O nodes than are remaining to be chosen.

Abstract: A digital filter, and more particularly a digital filter such as a transversal filter, is disclosed which is comprised of digital filter modules and provided with a function to detect the occurrence of anomalies such as overflow (a state in which excessively large or small absolute values exceeding an allowable limit are produced during arithmetic operations).

Abstract: A genlock frequency generation system synchronizes a dependent, or controllable, video source to an independent video source, with the capability of reverting to some predetermined default conditions in the event that no coherent independent video signal is found. The genlock frequency generation system is capable of placing a dependent video image in an arbitrary rectangular area overlaying the independent video image. Method and apparatus are disclosed.

Abstract: A digital filter, and more particularly a digital filter such as a transversal filter is disclosed, which is comprised of digital filter modules and provided with a function to detect the occurrence of anomalies such as overflow (a state in which excessively large or small absolute values exceeding an allowable limit are produced during arithmetic operations).