Patents Assigned to LSI Logic
  • Method for estimating a frequency-based ramptime limit
    Patent number: 7207021
    Abstract: A method is provided for selecting a frequency-based ramptime limit for a technology. The method includes creating a logic chain with cells from the technology and applying a sequence of signals to the logic chain. Each signal has a different ramptime relative to a clock period. At least one signal quality characteristic is measured along the logic chain for each of the signals. The frequency-based ramptime limit is selected based on a comparison of the measured signal quality characteristics measured to at least one predefined signal quality value.
    Type: Grant
    Filed: January 14, 2005
    Date of Patent: April 17, 2007
    Assignee: LSI Logic Corporation
    Inventors: Qian Cui, Chun Chan
  • High speed fully scaleable, programmable and linear digital delay circuit
    Patent number: 7205803
    Abstract: The digitally programmable delay circuit to correct timing skew between data and clock is developed. The digitally programmable delay circuit may be built by cascading delay cells. The delay circuit uses delay cells comprising simple digital elements such as inverters and tri-state inverters to eliminate the intrinsic delay and achieves linearity and monotinicity. The delay cell may be used as a building module which is repeatedly used in a serial fashion. The delay range is fully programmable from the delay of one delay cell to infinity if the chip area is available. The delay range can be scaled by adding more delay cells.
    Type: Grant
    Filed: June 29, 2004
    Date of Patent: April 17, 2007
    Assignee: LSI Logic Corporation
    Inventors: Tae-Song Chung, Hong Hao, Keven Hui
  • Method, apparatus and program for migrating between striped storage and parity striped storage
    Patent number: 7206991
    Abstract: A mechanism is provided for migration between stripe storage and redundant parity striped storage. When a disk is added to a disk array, the mechanism migrates from RAID 0 to RAID 5. For each row, the mechanism calculates parity for the row and, if the parity position is not the new drive, the mechanism writes the data from the parity position to the new drive and writes the parity to the parity stripe position. If a drive fails, the mechanism migrates back from RAID 5 to RAID 0. For each row, if the parity position is not the failed drive, reads the data from remaining drives, XORs the data stripes to get failed drive data, and writes the failed drive data to the parity position. If a read or write is received for the failed drive, the mechanism simply redirects the read or write to the parity position.
    Type: Grant
    Filed: October 15, 2003
    Date of Patent: April 17, 2007
    Assignee: LSI Logic Corporation
    Inventors: Paresh Chatterjee, Basavaraj Gurupadappa Hallyal, Senthil Murugan Thangaraj, Narasimhulu Dharanikumar Kotte, Ramya Subramanian
  • Selectable keying device
    Patent number: 7204371
    Abstract: A method and system for controlling electronic component configuration. The system includes a guard including an aperture and a plate including an aperture are adjustably connected. The guard and the plate each include a pin connected thereto. The system is capable of adjusting configurations to obtain an open configuration where at least a portion of the guard and plate apertures align and a blocked configuration where the plate and the guard apertures fail to permit access. Depending on an introduced component characteristic the component's physical keying structure may be received or prevented depending on the implementation. Additionally the present invention permits retrofitting a component with a correct characteristic but lacking a keying structure by disposing plate/guard pins outside the footprint of an introduced electronic component.
    Type: Grant
    Filed: July 9, 2002
    Date of Patent: April 17, 2007
    Assignee: LSI Logic Corporation
    Inventors: Terrill L. Woolsey, Tina M. Reintjes
  • Selectable and updatable computer boot memory
    Patent number: 7206971
    Abstract: A plurality of selectable memory devices is available for booting a computer processor. The devices may be selected prior to booting, or may be changed upon recognition that the booting process is not proceeding properly. In another use, one device may be reprogrammed with an updated version while keeping the older version present. Once the updated version is functioning properly, the older version may be overwritten so that two known working copies are available.
    Type: Grant
    Filed: April 7, 2003
    Date of Patent: April 17, 2007
    Assignee: LSI Logic Corporation
    Inventors: Jeremy R. Zeller, David E. Hoyer
  • Segmented addressable scan architecture and method for implementing scan-based testing of integrated circuits
    Patent number: 7206983
    Abstract: The present invention provides a segmented addressable scan architecture and method for implementing scan-based testing of integrated circuits. A scan chain is divided into a plurality of segments. For a test pattern, compatible segments of the plurality of segments are grouped into compatibility classes. All compatible segments or a subset of them within one of the compatibility classes are simultaneously loaded through selective activation.
    Type: Grant
    Filed: March 31, 2005
    Date of Patent: April 17, 2007
    Assignee: LSI Logic Corporation
    Inventors: Ahmad A. Alyamani, Mikhail I. Grinchuk, Erik Chmelar
  • Reduce or eliminate IMC cracking in post wire bonded dies by doping aluminum used in bond pads during Cu/Low-k BEOL processing
    Patent number: 7205673
    Abstract: A bond pad structure which includes an aluminum bond pad which include one or more dopants that effectively control the growth of IMC to a nominal level in spite of high tensile stresses in the wafer. For example, aluminum can be doped with 1–2 atomic % of Mg. Alternatively, Pd or Si can be used, or elements like Cu or Si can be used as the dopant in order to reduce the overall tensile stresses in the wafer. This can control the abnormal growth of IMC, thus arresting the IMC crack formation. A combination of dopants can be used to both control the tensile stresses and also slightly alter the gold-Aluminum interface thus enabling a uniform and thin IMC formation. This tends to reduce or eliminate any voiding or cracking which would otherwise occur at the wire bond transfer.
    Type: Grant
    Filed: November 18, 2005
    Date of Patent: April 17, 2007
    Assignee: LSI Logic Corporation
    Inventors: Jayanthi Pallinti, Dilip Vijay, Hemanshu Bhatt, Sey-Shing Sun, Hong Ying, Chiyi Kao
  • Method and/or circuit for implementing a zoom in a video signal
    Patent number: 7202911
    Abstract: An apparatus comprising a de-interlacer circuit, a rate converter circuit and a zoom circuit. The de-interlacer circuit may be configured to generate a first progressive signal having a first rate in response to an interlaced signal. The rate converter circuit may be configured to generate a second progressive signal having a second rate in response to the first progressive signal. The zoom circuit may be configured to generate an output video signal in response to the second progressive signal. The output video signal may represent a portion of the second progressive signal having a frame size equal to a frame size of the interlaced signal.
    Type: Grant
    Filed: November 24, 2003
    Date of Patent: April 10, 2007
    Assignee: LSI Logic Corporation
    Inventor: Herve Brelay
  • Systems and methods for wafer polishing
    Patent number: 7201633
    Abstract: An electromagnetic polish head (100) comprises at least one electromagnet. An embodiment may also include the addition of a slurry component or components that can be affected by an electromagnetic field. During polishing or planarization, a field or fields may be generated by the polish head (100) to affect the polishing of a wafer by attracting or repelling the slurry to a portion or portions of the substrate.
    Type: Grant
    Filed: February 22, 2005
    Date of Patent: April 10, 2007
    Assignee: LSI Logic Corporation
    Inventor: Robert Wayne Donis
  • Failure analysis and testing of semi-conductor devices using intelligent software on automated test equipment (ATE)
    Patent number: 7203877
    Abstract: The invention provides a number of related methods which improve the test and analysis of integrated circuit devices. A first method of the invention provides a method for pausing on a SCAN based test. A second method of the invention provides a method for using stimulations and responses of a known good device to increase fault coverage of patterns in a test flow. A third method of the invention provides a method to curve trace device buffers on an ATE.
    Type: Grant
    Filed: January 4, 2005
    Date of Patent: April 10, 2007
    Assignee: LSI Logic Corporation
    Inventor: Roger Yacobucci
  • Methods and structure for improved high-speed TDF testing using on-chip PLL
    Patent number: 7202656
    Abstract: Methods and structure for improved high-speed TDF testing using an on-chip PLL and associated logic to generate high speed launch and capture pulses. A reference clock may be applied to a PLL circuit within the integrated circuit under test to generate a higher frequency PLL Clock. Gating Logic features and aspects within the integrated circuit may apply the PLL Clock signal to a TDF Clock signal when so directed by a TDF Enable signal from an external test system. The PLL Clock is applied to the TDF Clock signal path for precisely two clock pulses for use as a launch and capture pulse sequence for TDF testing at higher speeds than the external automated test system may achieve.
    Type: Grant
    Filed: February 18, 2005
    Date of Patent: April 10, 2007
    Assignee: LSI Logic Corporation
    Inventors: Kevin Gearhardt, Douglas Feist
  • Wafer chucking apparatus for spin processor
    Patent number: 7201176
    Abstract: A wafer chuck is configured to hold a wafer efficiently for spin process cleaning of wafer edges and back sides. A first group of retractable tips extend to hold the wafer during a first portion of the cleaning period. A second group of retractable tips extend to hold the wafer during a second portion of the cleaning period. Residues left between the tips and the wafer edge areas during the first portion of the cleaning period are removed during the second portion. The change from the first group of tips to the second group of tips occurs while the wafer is rotating.
    Type: Grant
    Filed: April 11, 2006
    Date of Patent: April 10, 2007
    Assignee: LSI Logic Corporation
    Inventors: Kyoko Kuroki, Hideaki Seto
  • Spectral translation for VSB compensation
    Patent number: 7199843
    Abstract: A system for providing spectral compensation for vestigial sideband, VSB, signals with carrier frequency error. The VSB signal is sampled and digitized. The carrier frequency of the digitized signal is translated to a selected IF frequency. A fixed frequency VSB filter is then used to provide spectral compensation for the signal.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: April 3, 2007
    Assignee: LSI Logic Corporation
    Inventors: Dean Raby, Robert Caulfield
  • Sequential tester for longest prefix search engines
    Patent number: 7200785
    Abstract: The present invention is directed to a sequential tester for longest prefix search engines. The tester may include a longest prefix search engine, an inputs generator for providing a nearly random flow of input commands to the longest prefix search engine and for outputting a floating rectangle which may represent a search table of the longest prefix search engine, a coding module for providing address and prefix information to the longest prefix search engine, a mapping module for providing data information to the longest prefix search engine, a super search engine for performing super search operations, and an analyzer for computing predicted outputs of the longest prefix search engine and for comparing the predicted outputs with actual outputs computed by the longest prefix search engine.
    Type: Grant
    Filed: March 13, 2003
    Date of Patent: April 3, 2007
    Assignee: LSI Logic Corporation
    Inventors: Alexander E. Andreev, Anatoli A. Bolotov
  • RRAM memory timing learning tool
    Patent number: 7200826
    Abstract: A method of generating a timing model for a customer memory configuration, by generating a plurality of template memory netlists for a given RRAM design. Timing models for the template memory netlists are produced and stored in a first database. The template memory netlists are stored in a second database. A netlist for the customer memory configuration is generated and compared to the template memory netlists to find a match. When a match is found, one of the timing models that is associated with the matching template memory netlist is used as the timing model for the customer memory configuration. When a match is not found, two of the template memory netlists that bound the customer netlist are found, according to at least one parameter, and the timing model for the customer memory configuration is interpolated based on the two bounding template memory netlists.
    Type: Grant
    Filed: November 30, 2004
    Date of Patent: April 3, 2007
    Assignee: LSI Logic Corporation
    Inventors: Alexandre Andreev, Andrey Nikitin, Ranko Scepanovic
  • Method to monitor pad wear in CMP processing
    Patent number: 7198546
    Abstract: A pad groove analyzer and associated method configured to assess the grooves on the pad and determine how worn the pad is. The pad groove analyzer may be configured to monitor the grooves via a contact or no-contact process. In a contact process, the pad groove analyzer may include a stylus which physically contacts and moves along the pad. As the stylus falls into the grooves in the pad as the stylus moves along the pad, signals are created, and a stylus monitor uses the signals to determine to what extent the pad is worn. The stylus monitor can be configured to communicate with the general tool controller. In a no-contact process, the pad groove analyzer may take several different forms.
    Type: Grant
    Filed: June 29, 2004
    Date of Patent: April 3, 2007
    Assignee: LSI Logic Corporation
    Inventors: Michael Berman, Steven Reder, Matthew R. Trattles
  • Video horizontal and vertical variable scaling filter
    Patent number: 7197194
    Abstract: An apparatus for variably scaling video picture signals comprising a first circuit and a second circuit. The first circuit may be configured to generate one or more data signals vertically scaled to a first value in response to (i) the video picture signals and (ii) one or more control signals. The second circuit may be configured to generate one or more output signals horizontally scaled to a second value in response to (i) the one or more data signals and (ii) the one or more control signals. The first value and the second value are independently selectable.
    Type: Grant
    Filed: May 14, 2001
    Date of Patent: March 27, 2007
    Assignee: LSI Logic Corporation
    Inventor: Martin J. Ratcliffe
  • Method and structure for creating ultra low resistance damascene copper wiring
    Patent number: 7196420
    Abstract: A low resistance copper damascene interconnect structure is formed by providing a thin dielectric film such as SiC or SiOC formed on the sidewalls of the via and trench structures to function as a copper diffusion barrier layer. The dielectric copper diffusion barrier formed on the bottom of the trench structure is removed by anisotropic etching to expose patterned metal areas. The residual dielectric thus forms a dielectric diffusion barrier film on the sidewalls of the structure, and coupled with the metal diffusion barrier subsequently formed in the trench, creates a copper diffusion barrier to protect the bulk dielectric from copper leakage.
    Type: Grant
    Filed: October 26, 2005
    Date of Patent: March 27, 2007
    Assignee: LSI Logic Corporation
    Inventors: Peter A. Burke, Hongqiang Lu, Sey-Shing Sun
  • Floorplan visualization method using gate count and gate density estimations
    Patent number: 7197735
    Abstract: A method for floorplan visualization comprising the steps of (A) receiving design information for an integrated circuit design comprising one or more subsystems, (B) generating one or more gate count estimates for the one or more subsystems of the integrated circuit design, (C) generating one or more gate density estimates for gates of the one or more subsystems mapped to one or more programmable areas of a programmable platform device and (D) generating a visual representation of one or more area estimations for each of the one or more subsystems based on the one or more gate count estimates and the one or more gate density estimates.
    Type: Grant
    Filed: December 15, 2004
    Date of Patent: March 27, 2007
    Assignee: LSI Logic Corporation
    Inventors: Gregor J. Martin, Ying Chun He, Grant Lindberg
  • RRAM flipflop rcell memory generator
    Patent number: 7193905
    Abstract: An RRAM flip-flop rcell memory of the type having a write address decoder, a read address decoder, a set of n flip flops, one AND gate associated with each flip flop in the set, a set of w OR gates where each of the w OR gates in the set has n inputs, the improvement comprising only one write address decoder, and replacing the read address decoder and the set of AND gates and the set of OR gates with no more than one multiplexor, thereby providing a reduction in a path length from an rcell memory input to an rcell memory output and thereby improving timing of the rcell memory, while reducing fanout size of the rcell. In a preferred embodiment, the multiplexor includes fewer than w OR gates, and fewer than n AND gates, and two decoders, which are commonly connected to outputs of the n flip flops.
    Type: Grant
    Filed: October 25, 2005
    Date of Patent: March 20, 2007
    Assignee: LSI Logic Corporation
    Inventors: Alexander Andreev, Sergei Gashkov, Oleg B. Sedelev, Andrey Nikitin