Abstract: A packaged integrated circuit including a package substrate having electrical contacts for receiving an integrated circuit. The integrated circuit is electrically connected to the electrical contacts of the package substrate. A stiffener is mounted to the package substrate, where the stiffener has a non-orthogonal cut out in which the integrated circuit is disposed. The edges of the cut out are disposed at no greater a distance from the corners of the integrated circuit than they are from the sides of the integrated circuit.

Abstract: A circuit for stabilizing soft bits in a bit stream, the circuit having a first register to receive an initial read of the bit stream, a second register to receive a subsequent read of the bit stream, a comparator to compare the initial read of the bit stream to the subsequent read of the bit stream, a third register to receive a comparison string having bits set in positions where the initial read of the bit stream and the subsequent read of the bit stream do not match, indicating a soft bit in the positions, and an accumulator to receive the comparison string for multiple subsequent reads of the bit stream, and track positions of all soft bits detected during the multiple subsequent reads.

Abstract: A semiconductor package for a die with improved thermal cycling reliability. A first layer of the package provides ball pads dispersed throughout. A second layer of the package provides signal traces. A high stress area associated with the corner of the dies is defined. Preferably the high stress area is defined as two ball pitches away from the corner of the die. Signal traces are routed away from the high stress area and in particular signal traces are routed away from the ball pads associated with the high stress to eliminate the cracks in the routed traces.

Abstract: A method for processing a video bitstream is disclosed. The method generally includes the steps of (A) determining co-located motion information for a plurality of co-located sub-blocks in a co-located macroblock of the video bitstream, (B) storing the co-located motion information for (i) at least a first three of the co-located sub-blocks along a left side of the co-located macroblock, (ii) at least a second three of the co-located sub-blocks along a right side of the co-located macroblock and (iii) less than all of the co-located sub-blocks and (C) inferring current motion information for a current macroblock co-located in a different picture from the co-located macroblock using the co-located motion information that was stored.

Abstract: A circuit and method are presented for signal processing and routing of digital voice telephony signals, using a specialized high-density integrated circuit voice processor. The voice processor performs several essential functions required for telephony processing, including echo cancellation, protocol conversion, and dynamic range compression/expansion. These functions are traditionally performed by multiple circuits or modules. By combining these capabilities in a single device, power and circuit board area requirements are reduced. The embodiment of the circuit and method disclosed herein include novel implementations of a time-slot interchange circuit and a telephony signaling circuit. Both of these circuits are designed to minimize demands on the signal processing engines incorporated within the voice processor, and account for very little of the on-chip circuitry.

Abstract: Methods and associated structures for bypassing virtual memory and memory mapping management features provided in a memory controller applied to simpler computing applications. In one aspect hereof, simpler, embedded computing applications may utilize standard memory controllers including cash management and memory component interfacing features but may bypass virtual memory management features within the same memory controller component. Rather, features and aspects hereof intercept memory accesses generated by the memory controller for address translation features and perform simpler address substitution to apply an appropriate translated address to the system bus.

Abstract: A method for deinterlacing a picture is disclosed. The method generally includes the steps of (A) determining a protection condition by performing a static check on the picture in a region around a location interlaced with a first field of the picture, (B) calculating an interpolated sample at the location by temporal averaging the first field with a second field in response to the protection condition indicating significant vertical activity and (C) calculating the interpolated sample at the location by spatial filtering the first field in response to the protection condition indicating insignificant vertical activity.

Abstract: A semiconductor chip is provided which includes active and inactive IP cores. The spaces on the metal layer associated with the inactive IP cores includes voltage contrast inspection structures. The voltage contrast inspection structures serve to provide improved planarization of the metal layer and provided improved inspection capabilities.

Abstract: A method of stabilizing an identification series of bits by iteratively reading the identification series and logical OR'ing the identification series with a mask string after each read of the identification series. This produces a mask string having a first value in all positions of the mask string where bits in the identification series have never changed value during all of the readings of the identification series, representing stable bits, and a second value in all positions of the mask string where bits in the identification series have changed value during at least one of the readings of the identification series, representing unstable bits. The number of the unstable bits in the mask string having the second value is counted, and a method failure code is selectively reported when the number of unstable bits exceeds a maximum allowable number of unstable bits. An identification string is produced from the stable bits, and an identification code is calculated from the identification string.

Abstract: The present invention is a method and apparatus for providing iSCSI target stealth operation. In an exemplary aspect of the present invention, a method for prohibiting iSCSI discovery sessions may include the following steps: (a) receiving an iSCSI login request; (b) determining whether the iSCSI login request payload contains a “SessionType=Discovery” key/value pair; and (c) when discovery sessions are disabled and the iSCSI login request contains the “SessionType=Discovery” key/value pair, rejecting the iSCSI login request with a iSCSI status-class of “Target Error” and status-detail of “Session Type not Supported.” The present stealth mode may include the foregoing-described method for restricting the discovery operation and a method for managing discovery and ancillary protocols which may lead to denial of service attacks.

Abstract: The present invention is a disk drive power cycle screening method and apparatus for a data storage system. In an exemplary aspect of the present invention, a disk drive power cycle screening method for a data storage system includes: (a) selecting one or more drives in a disk array for power cycle screening; (b) transferring data contained in the selected one or more drives to at least one receiving drive in the disk array; (c) cycling power for the selected one or more drives; (d) verifying that the selected one or more drives function properly; and (e) returning the data from the at least one receiving drive to the selected one or more drives.

Abstract: An apparatus generally having a first circuit, a second circuit and a third circuit is disclosed. The first circuit may be configured to generate a plurality of difference values by calculating an absolute difference between each pixel from a current block and a corresponding pixel from a reference block substantially simultaneously. The second circuit may be configured to generate a plurality of sum values by adding the difference values. The third circuit may be configured to generate at least one motion vector in response to the sum values.

Abstract: A method is provided for transmitting serial data. The method includes receiving successive transmit data words, wherein each transmit data word has a plurality of bits. Each of the plurality of bits in each transmit data word is multiplied into a multiple number of adjacent bits to form an expanded data word. Each of the expanded data words is serialized to form a serial data word stream, which is transmitted.

Abstract: An improvement to an integrated circuit, of electrically conductive interconnects formed of a superconducting material. In this manner, the electrically conductive interconnects can be made very small, and yet still have adequate conductively. In various embodiments, all of the electrically conductive interconnects are formed of the superconducting material. In some embodiments, the electrically conductive interconnects are formed of a variety of different superconducting materials. In one embodiment, only the backend electrically conductive interconnects are formed of the superconducting material. In some embodiments no vias are formed of the superconducting material. The interconductor dielectric layers are preferably formed of silicon oxide, and sometimes all of the interconductor dielectric layers are formed of silicon oxide.

Abstract: The present invention provides a method and system for analyzing the quality of an OPC mask. The method includes receiving a target layer from a target design, receiving an OPC mask layer from the OPC mask. The method also includes classifying each cell of at least one of the target layer and the OPC mask layer as either repeating or non-repeating, and for each repeating cell, recognizing geometric points in the target layer to determine quality measuring groups. The method also includes simulating the OPC mask layer based on the quality measuring groups, measuring edge placement errors (EPEs) based on at least one of the geometric points, and providing an EPE layer representing EPEs greater than an EPE threshold.

Abstract: An apparatus comprising a first portion, a second portion and a processor. The first portion is configured to generate a count signal in response to a number of oscillations of a clock signal. The first portion is powered by an unswitched power source. The second portion is configured to generate an interrupt signal in response to the count signal and a predetermined stored value. The second portion is powered by a switched power source. The processor is configured to (i) receive the interrupt signal and (ii) generate the switched power.

Abstract: A system for RTL test insertion in an integrated circuit layout pattern includes a core module, a test wrapper, and a smart wrapper. The core module describes a function defined by logical elements, interconnections between logical elements, input pins and output pins. The test wrapper is adapted to encapsulate the core module and to create test pins representing the core module. The smart wrapper is adapted to encapsulate the test wrapper and to assign the test pins to a non-asserted state. The smart wrapper is adapted to place an assertion on one or more of the test pins for static or dynamic testing of the integrated circuit layout pattern.

Abstract: A method and apparatus for decoding and de-interleaving a received encoded and interleaved signal, the method employing and the apparatus including a single decoder coupled to a common buffer, the common buffer size equal to a frame of the received signal and the method further employing, and the apparatus further including, an address controller that causes data to be de-interleaved when read from the buffer and data to be interleaved when written to the buffer.

Abstract: The disclosure is directed to a method and apparatus for fixing hold violations in an integrated circuit design. The method and apparatus trace upstream along a path in the design corresponding to the hold violation, from an end point of the path toward a start point of the path, until an element is reached that corresponds to the start point or has a fanout exceeding a predetermined fanout limit. The method and apparatus then generate an output that defines a location in the design at which to insert a delay element, such that the delay element is connected to an input of an element downstream of the element reached during tracing.

Abstract: A method of retrieving a unique, repeatable identification value from an integrated circuit by identifying a plurality of state elements within the integrated circuit, where the state elements are part of standard functional circuitry within the integrated circuit, and are not part of a specialized circuit designed to primarily produce the unique, repeatable identification value, performing an initializing process on the state elements to bring the state elements to repeatable states, where the repeatable states of different state elements are dependent at least in part on differences between the different state elements, reading the repeatable states on the state elements, and joining the repeatable states into a binary number as the unique, repeatable identification value.