Abstract: A method for automated placement of markers or probe points adjacent to critical timing paths in an integrated circuit design. The markers aid in identifying critical path interconnect lines for purposes of failure analysis or design verification. In a method according to the invention, timing information related to various signal paths in an integrated path is analyzed to isolated critical timing paths. Once a signal path is determined to be a critical timing path, layout data for the critical path is extracted from a layout database. An unused area(s) is then located adjacent to the critical path. Marker information is next inserted into the unused area(s) of the layout database. The act of inserting marker information is performed by a specialized software tool capable of modifying a layout database. Alternatively, existing automated floorplanning or layout tools, or other electronic design automation (EDA) tools, whether proprietary or industry standard, are modified to insert the marker information.

Abstract: Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed.

Abstract: Pre-formatted MAC Control PAUSE frames are generated by a MAC device rather than by a switch. These may be automatically generated and transmitted upon the occurrence of a full or near full condition in the input buffer of the MAC device. The MAC device, upon receipt of a MAC Control PAUSE frame, allows a packet in the process of being transmitted to complete transmission prior to implementing the PAUSE. The MAC device is capable of generating MAC Control frames having any desired opcode. The parameter field associated with the MAC Control frame opcode is programmable. The destination address of the MAC Control frame is programmable. Automatic x-on/x-off is implemented. Flags may be set to enable/disable the IEEE 802.3x pause function in the MAC device and to override basic IEEE 802.3x operation in various ways.

Abstract: A method and apparatus of a synchronizer circuit for transferring signals between two clock domains in which a first synchronizer unit and a second synchronizer unit form a hand-shaking protocol. In particular, an input event from a source clock domain is captured in an input unit and a first signal is asserted indicating that the input signal is to be transferred to a target clock domain. This first signal is synchronized to the clock signal in the target clock domain at the first synchronizer unit, causing assertion of a second signal. The second signal is coupled to an output unit which generates an output event signal for a single clock period.

Abstract: A silicon semiconductor integrated circuit includes an insulative field oxidation layer which substantially does not encroach under active circuit elements of the integrated circuit. The field oxidation layer is formed of oxidized amorphous silicon created by bombardment of a silicon substrate with noble gas ions. The amorphous silicon oxidizes at a rate much faster than crystalline silicon so that when the field oxidation layer is formed crystalline silicon foundations for the active circuit elements are left substantially intact. The crystalline silicon foundations are formed by using appropriate shield elements during the noble gas ion bombardment. This noble gas ion bombardment also has the advantage of eliminating dislocation defects which may be present in the field oxidation area so that these defects do not propagate into the crystal lattice of the silicon during subsequent heating and cooling cycles.

Abstract: High voltage tolerant thin film transistors (TFTs) may be formed during a dual work function polysilicon process used to fabricate poly--poly capacitors with substantially no additional process complexity. Polysilicon lower plate material is patterned in those areas targeted for TFT formation into source, drain, and channel regions. In one embodiment, TFT source and drain regions are doped to the same conductivity as capacitor lower plate regions while TFT channel regions are not doped. In another embodiment, TFT channel regions are lightly doped with positively charged ions. Capacitor dielectric material is used to form TFT gate structures. Capacitor top plate silicon provides TFT gate connection surfaces.

Abstract: A conditioning wafer for conditioning a polishing pad employed in chemical-mechanical polishing of an integrated circuit substrate is described. The conditioning wafer includes a disk having a conditioning surface and a plurality of abrasive particles secured on the conditioning surface of the disk. Furthermore, the abrasive particles engage with the polishing pad when the conditioning wafer contacts the polishing pad during conditioning of the polishing pad.

Abstract: A method of forming a layout definition of a semiconductor integrated circuit includes generating a netlist of functionally committed standard cell instances and the electrical interconnections between the standard cell instances. The standard cell instances are then placed in a layout pattern. Also, functionally uncommitted base cells are place with the standard cell instances in the layout pattern. The base cell instances may be metalized, if needed, in later processing steps to implement design changes by adding additional logical functions.

Abstract: A method for automatically terminating a bus that is dependent upon whether devices are coupled to ports of a device interface is disclosed. The method includes the steps of (a) generating a first sensing voltage having a voltage level equal to one of at least three levels; (b) generating a first control voltage having a fourth level when the voltage level of the first sensing voltage has a first predetermined logical relationship to a first reference voltage; and (c) terminating a first plurality of lines of the bus at the device interface when the first control voltage is equal to the fourth level. An apparatus suitable for implementing the above method is also disclosed.

Abstract: A system for providing information to memory within a local device is provided herein. The system initially receives information transmitted from a remote location and reads predetermined data, including start and end addresses, within the local device. The system computes a checksum based on information received from the remote location and the predetermined data and compares a predetermined checksum to the received information checksum. If the predetermined checksum does not equal the received information checksum, the system requests retransmission of information and repeats the preceding steps (receiving information, computing a checksum, and comparing) until the predetermined checksum equals the received information checksum. The system then provides the valid information to local device memory. The invention may execute a protocol to receive information packets and store the information packets in appropriate memory locations after receiving the information.

Abstract: An improved DBS receiver front end architecture having a tuner chip and a demodulator/decoder chip. The tuner chip and the demodulator/decoder chip each include portions of a digital tuning frequency synthesizer. The frequency synthesizer comprises one or more digital counters which are implemented on the demodulator/decoder chip, and an oscillator which is implemented on the tuner chip. This advantageously avoids digital noise interference with the tuner chip while providing a reduced part count. Briefly, the present invention concerns a DBS receiver front end which includes a tuner chip and a demodulator/decoder chip which cooperate to perform a frequency synthesis function. The tuner chip has a tuning oscillator coupled to a tank circuit having an adjustable resonance frequency, and a downconverter coupled to receive a tuning frequency signal provided by the tuning oscillator.

Abstract: A direct memory access (DMA) controller transmits and receives formatted data frames having frame headers in a communications subsystem. The DMA controller includes a transmit input and output, a receive input and output, transmit circuitry, receive circuitry, a receive frame header capture circuit, a receive frame action table and a response message table. The transmit circuitry receives transmit data frames on the transmit input and applies the transmit data frames to the transmit output. The receive circuitry receives receive data frames on the receive input and applies the receive data frames to the receive output. The receive frame header capture circuit obtains a frame header from the received data frames and applies the frame header to the receive frame action table. The receive frame action table generates a frame action command based on the frame header field.

Abstract: When a mobile communication unit (e.g. a cellular telephone) is powered up, the unit must lock on to a local base station, or "acquire" a base station signal, to enable the user to send and receive calls. To lock on a local base station, the mobile unit must determine the delay at which the base station is sending the pseudo random (PN) code. This process is called the "acquisition." The current art of acquiring a base station involves collecting a set of samples at a particular code phase, or delay, testing the collected sample, and repeating these steps using another code phase until the correct code phase is found. The present invention discloses a method and apparatus for collecting a set of samples at a particular code phase, and simultaneously testing the collected sample and collecting the next set of samples for another code phase.

Abstract: A capacitor that is a metal to polysilicon capacitor. The capacitor is fabricated by forming a field oxide layer on a substrate. Then, a polysilicon segment is formed on the field oxide layer. This polysilicon segment forms a polysilicon bottom plate for the capacitor. A dielectric layer is formed and planarized. An opening is made in the dielectric layer to expose a portion of the polysilicon segment. Then, an oxide layer is formed on exposed portions of the polysilicon segment. A metal segment is formed on the oxide layer over the opening, wherein the metal segment forms a top-plate for the semiconductor device.

Abstract: A DRAM cell capacitor is described. Capacitor formation and cell insolation methods are integrated by using existing isolation trench sidewalls to form DRAM capacitors. A doped silicon substrate adjacent to the vertical sidewalls of the isolation trench provides one DRAM cell capacitor plate. The DRAM capacitor also contains a dielectric material that partially covers the interior vertical sidewalls of the isolation trench. A conductive layer covering the dielectric material on the vertical sidewalls of the isolation trench forms the second capacitor plate and completes the DRAM capacitor.

Abstract: A method for mounting an integrated circuit includes a plurality of solder balls arrayed on the bottom surface of a package of the integrated circuit onto to a circuit board. These solder balls provide for surface mounting of the integrated circuit to a circuit board by solder reflow. The array of solder balls can be planarized so that each of the plural solder balls participate in defining a truly planar solder ball contact array for the integrated circuit package. Methods of manufacturing the integrated circuit with a package having planarized solder balls in an array dependent from a bottom surface thereof are set forth. The truly planarized solder ball contact array of the integrated circuit package affords nearly absolute reliability in forming of surface-mount electrical connections between the integrated circuit package and the circuit board on which the package is to mount.

Abstract: A modified chemical-mechanical polishing apparatus is described. The apparatus includes: (i) a polishing pad 104 providing a surface against which a surface of an integrated circuit substrate 116 is polished; (ii) an anode 103 on which the polishing pad is secured, the anode including an electrolyzable conductive material; and (iii) a voltage source 106 electrically connecting the anode to the integrated circuit substrate in such a way that when a voltage is applied from the voltage source in the presence of slurry 114 admixed with an electrolyte composition on the polishing pad, an electrolytic cell results in which the conductive material deposits on the surface of the integrated circuit substrate. A process of depositing a conductive material on and polishing a surface of an integrated circuit substrate simultaneously is also described.

Abstract: A write-through data cache which incorporates a line addressable locking mechanism. By executing a software lock instruction or unlock instruction, a microprocessor controls the locking or unlocking of individual cache lines in the data cache. A locked cache line is not subject to deallocation. By locking a plurality of lines in the data cache, the microprocessor configures a reserved area of guaranteed fast access memory within the data cache. The data cache includes a mechanism to disable write-through of write requests on a line addressable basis. By executing a software write-through disable instruction, the microprocessor commands the data cache to disable write through operations on an individual cache line. By disabling write-through on cache lines which have been locked, the plurality of locked lines behaves like a true fast-access internal memory with guaranteed access time: write requests targeting the reserved area of locked lines are not written through to the bus interface.

Abstract: A method for composing a low dielectric thermally conductive thin film is disclosed. A layer of precursor material is first deposited on a silicon substrate. Without affecting its structure and porosity, the layer of silica precursor material is then dried and becomes a layer of porous silica film. Subsequently, the silicon substrate is exposed to a methane gas atmosphere at a temperature of approximately 200-350.degree. C., during which methane gas molecules are oxidized locally to liberate carbon atoms. Some of the liberated carbon atoms will bond to the interior of the porous silica film. The carbon atoms from the methane gas molecules then permeate the nanopores within the porous silica film such that the entire nanostructure of the porous silica film is carbidized. As a result, a composite porous silica film, which may serve as a dielectric layer within an interconnect structure, is formed.

Abstract: A test circuit includes a writing unit that outputs m-bit data captured upon receipt of a clock signal, branches the m-bit data n identical m-bit data signals, and stores the n m-bit data signals in a memory device. A function determining unit reads the n m-bit data signals from the memory, compares one of the n m-bit data signals to an m-bit expected value, and determines coincidence or non-coincidence between the n m-bit data signal and an expected value.