Abstract: A processor is implemented with an operand register file having N operand registers, instructions that reference these operand registers with virtual and physical source and destination addresses of variable up to n addressing dimensions, and at least one address mapping circuit that maps the uni-dimensional virtual and the multi-dimensional virtual/physical source and destination addresses to their uni-dimensional equivalents. Whether a source/destination address is a virtual or a physical address may be implicitly inferred from the instruction type, or explicitly specified. Source and destination addresses of an instruction may be either all virtual addresses, or all physical addresses, or virtual as well as physical addresses. The addressing dimension of an instruction's source and destination addresses may be specified in the instruction, or specified in a control register of the processor.

Abstract: An electrostatic digitizing panel capable of filtering offset loads such that stylus or fingertip position information is more accurately obtained. The present invention utilizes a new method of calculating the stylus position such that the digitizer surface is sensitive only to the electric field concentrated in the area occupied by the stylus or fingertip. Thus, the panel has a substantially reduced sensitivity to fields emitted from a user's hand or noise fields emitted from the surface of a display, or the like, coupled to the panel.

Abstract: A semiconductor memory device capacitor is disclosed which has a trench capacitor portion provided in a semiconductor substrate and a fin capacitor portion provided above the substrate. The trench capacitor portion includes (i) a trench extending from an upper surface of the semiconductor substrate downwardly into the substrate, and (ii) an electrically conductive trench electrode provided interior to the trench. And the fin capacitor portion includes (i) a fin electrode having a body portion and two or more electrically conductive fins extending outwardly from the body portion, (ii) a fin dielectric layer conformally coating the two or more electrically conductive fins, and (iii) a cell electrode surrounding and in intimate contact with the two or more electrically conductive fins.

Abstract: A Fibre Channel network is provided with an efficient implementation of the loop initialization process. In one embodiment, the network comprises nodes coupled by unidirectional serial communications links in a ring topology. The nodes typically include a serial communications transceiver, a transmit controller, a receive controller, and a memory unit. The serial communications transceiver operates to drive transmit signals on the outgoing serial communications link and to buffer receive signals from the incoming serial communications link. The memory unit includes transmit and receive buffers that are coupled to the transceiver via transmit and receive controllers. One or more of the nodes may also include a control register having an "autoswap" bit. The autoswap bit is initially reset to 0 when the node enters the initialization mode.

Abstract: A repeating cell structure in a semiconductor substrate for a BiCMOS logic gate array. The cell structure has three regions shaped as columns. The first columnar region is a P-well and has four vertically aligned active areas of N-type material formed within the columnar region. Each of the active areas has two gate electrodes to form two NMOS transistors. Similarly the second columnar region is a N-well and has four vertically aligned active areas of P-type material. Each such active region forms two PMOS transistors. The third column has two bipolar transistors, each with collector, base and emitter regions vertically aligned. The resulting BiCMOS logic array permits a flexible location of macrocells, which results in a compact implementation of the resulting integrated circuit.

Abstract: A method and apparatus for fast decoding of a Reed-Solomon codeword which includes storing the codeword in memory, finding syndromes of the codeword, using the syndromes to determine the number of errors in the codeword, which in turn are used to find an error locator polynomial for the codeword, which is a polynomial whose roots can be used to find the locations of the errors. This error locator polynomial is then be used to find the positions of the errors in the codeword. The positions of the errors in the codeword can be used along with the syndromes to determine the values of the errors in the codeword.

Abstract: A method of simulating a masking process in which a process simulator is used to produce an aerial image. The simulator is configured to receive input information. The input information includes a digital representation of a patterned mask and a data set. Each element of the data set corresponds to one of a plurality of parameters associated with the masking process. The simulator is configured to produce an aerial image based upon the input information. The aerial image represents the simulator estimation of a pattern that would be produced by the masking process using the patterned mask under conditions specified by the data set. The method further includes the step of supplying the input information to the simulator to produce the aerial image. A first data base is then generated from the aerial image. The first data base is a digital representation of the aerial image. Thereafter, the pattern is produced on a semiconductor substrate using the masking process and the patterned mask.

Abstract: A storage target device controller (such as an embedded controller in a SCSI disk drive) processes multiple commands concurrently in accordance with the methods and structures of the present invention. Each command is stored within its own context within the target device controller to retain all unique parameters required for the processing of each command. Processing of multiple commands permits switching of command contexts within the target device to improve utilization of resources associated with the target device. For example, when a first, active, command context is prevented from further processing due to the status of the disk channel, an inactive command context may be swapped with the active command context to better utilize the host channel communication bandwidth. Similarly, a first active command context may be configured to automatically switch to a linked command context upon completion of processing to further ease management of multiple contexts.

Abstract: A data transfer device for transferring packets of data across an asynchronous boundary separating a first time domain from a second time domain, and, a method for transferring the packets of data is disclosed. The device comprises a plurality of transmitter/receiver combinations, which form a plurality of channels across the asynchronous boundary, such that multiple packets of data can be transferred across the asynchronous boundary at any one time. The device comprises ordering units which preserve the order of the packets of data as they are transferred across the asynchronous boundary. The ordering units perform this function by transmitting the packets of data through transmitters in a predetermined transmitter sequence and receiving the packets of data on the receivers in a predetermined receiver sequence which corresponds to the predetermined transmitter sequence. In this way, the predetermined order of the packets of data being transferred across the asynchronous boundary is preserved.

Abstract: Electronic system utilizing semiconductor devices having heat dissipating leadframes are provided by using materials, such as copper, which exhibit good thermal and electrical conductivity, and arranging the lead fingers of the leadframe in a configuration which provides good thermal coupling with the surface of a semiconductor die. Micro-bump bonding techniques are employed to provide additional thermal coupling at the electrical connection point of the leadframe fingers to the die. Leadframe fingers exhibiting a high aspect ratio (height:width) are described. Leadframe fingers extending substantially beyond interior bond pads are described.

Abstract: A bi-directional transfer device for transferring packets of data across an asynchronos boundary separating a first time domain includes control logic which utilizes a single handshake signal to both request that the first time domain receive a packet of data from the second time domain, and, acknowledge receipt of an immediately previous packet of data by the second time domain from the first time domain. The device is bi-directional in that for each packet of data sent from one time domain, a corresponding packet of data should then be received from the other time domain. If one time domain has several more packets of data to send than the other time domain, the time domain with fewer packets of data sends invalid packets of data and asserts a signal indicating that the packets of data are invalid. The device is expandable such that two or more packets of data can be simultaneously exchanged across the asynchronous boundary.

Abstract: A method of polishing a first layer of a semiconductor wafer down to a second layer of the semiconductor wafer is disclosed. One step of the method includes heating a back surface of the semiconductor wafer to a first temperature level so as to cause a front surface of the semiconductor wafer to have a second temperature level. Another step of the method includes polishing the semiconductor wafer whereby material of the first layer is removed from the semiconductor wafer. The polishing step causes the second temperature level of the front surface to change at a first rate as the material of the first layer is being removed. The method also includes the step of halting the polishing step in response to the second temperature level of the front surface changing at a second rate that is indicative of the second layer being polished during the polishing step. Polishing systems are also disclosed which detect a polishing endpoint for a semiconductor wafer based upon heat conducted through the semiconductor wafer.

Abstract: A method of simulating a masking process in which a process simulator is used to produce an aerial image. The simulator is configured to receive input information. The input information includes a digital representation of a patterned mask and a data set. Each element of the data set corresponds to one of a plurality of parameters associated with the masking process. The simulator is configured to produce an aerial image based upon the input information. The aerial image represents the simulator estimation of a pattern that would be produced by the masking process using the patterned mask under conditions specified by the data set. The method further includes the step of supplying the input information to the simulator to produce the aerial image. A first data base is then generated from the aerial image. The first data base is a digital representation of the aerial image. Thereafter, the pattern is produced on a semiconductor substrate using the masking process and the patterned mask.

Abstract: A cache controller with an improved cache memory refill operation is presented. After a request from a CPU for a word of information and the word is not found in the cache memory, the cache controller starts a refill operation by which a line of information including the requested word is loaded into the cache memory from a main memory. The cache controller keeps track of the CPU requests. When a requested word appears during the refill operation, the CPU is notified to load the requested word as the word is loaded into the cache memory. Furthermore, the cache controller efficiently takes advantage of free cycles in the refill operation. If the CPU has requested a word in the cache memory, the cache controller reads the word from the cache memory so the CPU can load the word during a free cycle.

Abstract: A single-chip synchronous optical network (SONET) physical layer device includes first, second and third interface ports. An asynchronous transfer mode (ATM) interface circuit is coupled to the first interface port. A point-to-point protocol (PPP) processing circuit is coupled to the second interface port and the ATM interface circuit. A SONET framer circuit is coupled between the ATM interface circuit and the third interface port and between the PPP processing circuit and the third interface port. The device is programmable to allow multiple standard and non-standard data transmission modes, including transmitting ATM cells in SONET payloads; PPP frames in ATM cells in SONET payloads, PPP frames from a UTOPIA interface in SONET payloads and PPP frames directly in SONET payloads.

Abstract: Integrated circuit chips (IC's) require proper placement of many cells (groups of circuit components) and complex routing of wires to connect the pins of the cells. Because of the large number of the cells and the complex connections required, it is essential that placement of the cell and the wire routine be done correctly to avoid any congestion of wires. The present invention discloses method and apparatus to optimize the cell density of the segments of columns on the IC. To optimize the segment or column density, the present columns densities are calculated, and the desired densities are determined. Then, the amount and the location of the of cell overload is found. The cells of the overloaded columns are spread out the neighboring columns. The reassignment of the cells are performed to minimize the distance, therefore the affect, of the relocation.

Abstract: An apparatus for polishing a first side of a semiconductor wafer down to a desired level includes a polishing platen having a polishing surface. The polishing platen has a light egress opening defined therein. The apparatus also includes a wafer carrier which is configured to engage the wafer by a second side of the wafer and apply pressure to the wafer in order to press the wafer against the polishing surface of the polishing platen, wherein the wafer carrier has a light-ingress opening defined therein. The apparatus further includes an infrared light source unit positioned such that light signals generated by the infrared light source unit are directed out the light egress opening and into the wafer. The apparatus yet further includes a light receiving unit positioned such that the light signals generated by the infrared light source unit emanate out of the wafer and are received with the light receiving unit.

Abstract: A fabrication method for an electrically programmable read only memory device, which consists of a control/word gate and a floating gate on the side wall of the control gate. The unique material selection and blocking mask sequences allow simple and safe fabrication within the delicate scaled CMOS process environment, of a side wall floating gate with an ultra short channel under the floating gate, which involves double side wall spacer formation i.e., a disposable side wall spacer and the final polysilicon spacer gate.

Abstract: A system for externally monitoring the angular rotation rate of a spin rinse dryer chamber in a semiconductor fabrication facility. The system includes a spin rinse dryer comprised of a dryer housing and a chamber wall that is capable of rotating within the housing. The chamber wall defines a chamber suitable for receiving a designated wafer carrier. The dryer further includes a chamber door hinged to the housing for enclosing the chamber. The spin rinse dryer is configured to rotate the chamber when activated. A detection apparatus of the system is positioned externally to the dryer housing in proximity to the chamber. The detection apparatus is adapted to detect the angular rotation rate of a detectable marker affixed to an exterior wall of the designated wafer carrier when the designated wafer carrier is placed in the chamber and the spin rinse dryer is activated.

Abstract: A substrate holder assembly for forming a substantially uniformly polished substrate surface during chemical-mechanical polishing is described. The substrate holder assembly includes a carrier film having: (A) a porous layer with (i) a first surface with an outwardly protruding dome shaped region that applies pressure on at least a portion of the substrate surface during chemical-mechanical polishing and a location of the protruding dome shape is aligned with a location of an area of substrate surface that is likely to be underpolished, (ii) a second surface facing a contact surface of a backing plate; and (B) a pressure sensitive adhesive backing layer for affixing the carrier film to the contact surface of the backing plate under sufficient pressure.