Abstract: A system in which logic and/or memory elements are automatically placed on an integrated circuit ("floorplanning") taking into account the constraints imposed by the logic designer, not only increase the density of the integrated circuit, and the likelihood of routing interconnections among the elements on that circuit, but it also enables the user to quickly modify the floorplan manually, and then graphically display the results of such modifications. By conforming itself to the logic designer's modular, hierarchical design, the system is capable of placing elements at each level of the specified hierarchy, based upon the number of interconnections between elements throughout that hierarchy.

Abstract: An integrated circuit (IC) chip package is formed by extending the overall dimensions of a standard IC on a semiconductor substrate, typically a first silicon wafer, to provide an integral band of semiconductor material therearound on which are formed a series of spaced IC chip input/output pad areas extending along the band. A bottom peripheral edge of a discrete cap of the same semiconductor material, e.g. silicon, is sealingly affixed around an inner periphery of the band inboard of the series of pad areas and outboard of the IC active circuit areas, so that the cap interior spacedly covers the active circuit area and the input/output pad areas are exposed. The caps may be made by photolithography and microetching techniques from a second semiconductor wafer of the same type as the IC wafer. Metallization extends on the first wafer from connect pads on the active circuit area to the extended and exposed input/output pad areas exterior of the cap. The IC may be probed for test purposes prior to capping.

Abstract: Disclosed is a simulation model which facilitates the "real-time" simulation of application specific integrated circuits (ASICs) in the actual digital computer system in which they will be incorporated. Significantly, this invention permits the emulation of an ASIC device, and thus does not require the fabrication of an actual physical specimen of that device. Instead, this invention permits the use of a software model which facilitates debugging of the ASIC device and permits effective generation of system test vectors. Such an approach facilitates the system-level testing of ASIC devices prior to fabrication, by permitting both the generation of system test vectors and the debugging of the internal behavior of such ASIC devices without limiting the flexibility, with respect to other devices in the system, of either simulating such devices in software or utilizing actual physical specimens of such devices.

Abstract: This invention provides trans-3,4 1-substituted-3-substituted-4-methyl-4-(3-substituted phenyl)piperidines as opioid antagonists capable of blocking the mu or kappa receptors in the brain.

Abstract: An improved package with J-leads for an integrated circuit is obtained by modifying the package profile so as to relieve the bottom edge to provide space for insertion of a rod to be used as a tool to shape or reshape the curved part of the leads. This permits both easier original manufacturing and faster and better reshaping of bent leads.

Abstract: A gate array is provided in which active areas within the substrate are arranged in alternating columns of opposite conductivity type and symmetrical about the center lines through each column so that CMOS devices can be advantageously formed by allocating only small increments of active area to metal routing. The substrate and well taps are also symmetrical about the column center line. The active area symmetry allows p-channel and n-channel transistors to be combined where the p-channel transistor is on either the right or left, thus increasing the flexibility in placing the elements within the integrated circuit chip.

Abstract: A method for forming a multilayer integrated circuit is described wherein the resultant top surface thereof is substantially planar. The method involves first forming a layer of connecting metallization on integrated circuit components formed in a conventional manner. Then a first layer of dielectric is formed on the metallization layer. Next a second dielectric layer is formed on the first dielectric layer. Via areas are then formed by etching the first and second dielectric layers in order to expose selected areas of the first metallization layer, and filled with metal to form vias. A layer of photoresist is deposited on all surfaces. Lastly, the surface is etched using an etchant that etches dielectric, metal and photoresist at substantially the same rate such that said vias are exposed and a planar top surface produced.

Abstract: A general purposes architecture for a digital microcomputer, which includes a central processing unit, random access memory, user-defined dedicated functions and an optional programmable read only memory. Instructions are fetched either externally or from the optional ROM. Data can be fetched externally or internally. Each instruction fetched is interpreted by a general-purpose microengine. The architecture is flexible enough to permit the modular addition, deletion and modification of dedicated functions and macroinstructions (including changes in execution timing and decoding), as well as the testing of memory independently from the rest of the architecture.

Abstract: A CMOS driver circuit for integrated circuits capable of operating in two modes. The first, high speed, mode allows the driver circuit on an integrated circuit device to drive the internal signals of the device to the outside world for standard operation of the integrated circuit devices. The second mode causes the driver circuit to behave as a weak driver for easily testing the integrated circuit.

Abstract: An interchangeable shelf support bracket (10) particularly for use with either one of two different thicknesses of shelves includes a side plate (12), mounting pins (14), edge flange (16), and pair of opposing retainer tabs (22, 24) each of which includes a lip (b 26, 28) adapted to receive the edge of one of the two shelves.

Abstract: A circuit (40) constructed in accordance with this invention includes a ring oscillator (25) to provide a signal which is dependent on the propagation delays of the inverters (33, 34, 35) comprising the ring oscillator, therefore the frequency of the ring oscillator is inversely dependent upon the propagation delays of the inverter comprising the ring oscillator. Means (37) are provided to determine the propagation delay introduced by the components in the ring oscillator by measuring the frequency of the output signal produced by the ring oscillator which provides a signal to a multiplexer (36) which selects among a number of preset delay components (26) those components which are necessary to ensure that the propagation delay caused by the circuitry (not shown) connected to the input lead (21) of the circuit constructed in accordance with this invention plus the propagation delay introduced by the selectable delay elements is nearly a constant propagation delay.

Abstract: A composite support assembly for an integrated circuit chip includes a rigid lead frame that is attached to a relatively thin flexible tape-like structure. The tape-like structure is etched with inner lead fingers and outer lead fingers to allow a short pitch, high density arrangement of the lead fingers, thereby enabling bond wires that connect an IC chip to the support assembly to be shortened. As a result, a significant increase in the number of leads is realized, using a standard size IC package.

Abstract: Bonding of lead wires between electrical contact points of an integrated circuit and the conductive elements of a flexible tape-like structure on which the integrated circuit is seated is accomplished by means of a vacuum chuck having distributed recesses through which a partial vacuum is applied to the flexible structure. Support elements are provided with the vacuum recesses to ensure that the flexible tape-like structure presents a planar orientation to a bonding tool. The tape-like structure is maintained in a substantially rigid position during the bonding process enabling precision bonding of lead wires.

Abstract: A read/write method using a non-contact system and used between a storage substrate and a read/write unit, the method including a storage substrate providing a memory at a card or other substrates, and a read/write unit, the storage substrate providing a coil for power supply, a coil for receiving data to be recorded in a memory, a coil for outputting toward the read/write unit the data recorded in the memory, and a coil for receiving a mode command, the read/write unit providing coils corresponding to four coils at the storage substrate, so that the respective corresponding coils at the storage substrate are insertably positioned in the magnetic flux generated by each coil at the read/write unit, whereby the read/write unit writes data in the memory at the storage substrate, or the data stored in the memory at the storage substrate is read by the read/write unit.

Abstract: A Gray code counter employs modules of binary bits to form expressions or numbers. The count is sequenced from one expression to the next by changing only one binary bit in one location of an expression. The Gray code counter can be an incrementing counter or an increment/decrement counter. The counter can operate with expressions of several bits, and employs a minimal number of D type flip-flops and logic gates.

Abstract: A bus interface system for communicating between a master bus interface and a plurality of slave bus interfaces includes a plurality of lines extending between the master unit and each of the slave units, the lines including a clock line containing clock signals, a gated clock line containing gated clock signals having a frequency which is a submultiple of the frequency of the clock signals, a data line, a command register line, an active line, and circuitry for exchanging data between the master unit and one of the slave units on the data line under the control of the other lines.

Abstract: The present method provides for formation of isolation oxide without "bird-beak" extensions thereof through the use of a nitride mask in contact with the surface of a semiconductor substrate on both sides of a patterned oxide layer, on which substrate the isolation oxide is grown.

Abstract: An integrated circuit devicer package includes a rigid frame and flexible tape assembly having wire leads between the die attach pad, conductive lead fingers, and the I.C. chip. A dam structure prevents resin flow to ensure proper wire bonding and a wedge prevents electrical shorting. A recognition pattern enables precise wire bonding. A epoxy molding compound is interposed in cavities formed in a Kapton layer to preclude delamination.

Abstract: A circuit (40) constructed in accordance with this invention includes a ring oscillator (25) to provide a signal which is dependent on the propagation delays of the inverters (33, 34, 35) comprising the ring oscillator, therefore the frequency of the ring oscillator is inversely dependent upon the propagation delays of the inverter comprising the ring oscillator. Means (37) are provided to determine the propagation delay introduced by the components in the ring oscillator by measuring the frequency of the output signal produced by the ring oscillator which provides a signal to a multiplexer (36) which selects among a number of preset delay components (26) those components which are necessary to ensure that the propagation delay caused by the circuitry (not shown) connected to the input lead (21) of the circuit constructed in accordance with this invention plus the propagation delay introduced by the selectable delay elements is nearly a constant propagation delay.

Abstract: A process for forming vias in semiconductor structures includes the step of forming a pillar on an underlying dielectric layer prior to deposition of the metallization layer. The pillar is located above the diffusion region preferably and serves to provide substantially equal distances or heights for etching vias from the top planarized surface to the metallization layer deposited over the field oxide region and over the diffusion region.