Abstract: A system for aligning a semiconductor wafer with a mask bearing a pattern to be formed on the wafer, in which both the wafer and the mask bear an alignment mark, and in which light used for alignment is filtered to transmit only in a selected bandwidth, uses a reflector system to gather light reflected from edges of the alignment mark on the wafer. In order to minimize the effect of erroneous alignment signals from standing waves generated when the alignment signal is reflected from a wafer coated with a layer of photoresist, a second filter is placed in the path of light after it has reflected from the target. This second filter transmits a range of the reflected light which does not produce standing waves.

Abstract: A CMOS reset circuit has a reverse biased diode and a latch for latching a p-channel enhancement mode MOSFET on during the first part of the power-on cycle. The p-channel MOSFET is part of a voltage divider which also includes a resistor. When the voltage between p-channel MOSFET and resistor reach the threshold of an n-channel enhancement mode MOSFET, the p-channel MOSFET is switched off. Reset pulses are provided through one or two inverters by a load on the latch.

Abstract: A contact (15) formed in accordance with the present invention includes rounded corners on the upper and lower surface and sloped walls in the dielectric material (10) in which the contact is formed. In one embodiment, a photolithographic mask is formed above the dielectric material (10) using photolithographic techniques well known in the art. Using reactive ion etching techniques, the contact is etched until a small portion of the dielectric material remains to be etched in the contact. The photolithographic mask is then removed. The contact is then completely etched using a reactive ion etching process. Using this technique, the contact formed has rounded upper edges.

Abstract: A modular system (30) for framing and supporting work surfaces and storage units includes a pair of generally rectangular end frames (32) having side member (36) each defining inside and outside channel sections. The end frames (32) are releasably secured together by lateral connectors (34) which are adjustably clamped along the inside channel portions of the end frame side members (36). The lateral connectors (34) are adapted for supporting storage units by means of inverted J-shaped hooks 70. The work surfaces are independently supported on arms (84) which are adjustably clamped along the outside channel sections of the end frame side members (36) in order to facilitate rearrangement and adjustment in accordance with the requirements of laboratories and the like. A modular system (120) adapted for use with existing structural walls (128) is also disclosed.

Abstract: An improved tracer ammunition round and method of manufacturing the tracer ammunition is disclosed. Each round is fabricated by first providing an elongated hole in a cord of soft metal, filling the hole with a special pyrotechnic composition and then reducing the diameter of the cord to a desired size. The cord is then cropped into round size lengths and each length is treated to provide a shaped slug with a pyrotechnic column throughout its length. The shaped slugs are then inserted into the interior cavities of shaped metallic jackets and are secured therein by crimping. The pyrotechnic column is formed of zirconium powder, potassium perchlorate and a suitable binder. The ratio of the length of the column to its diameter is between five and two hundred and the diameter of the pyrotechnic column is between 0.025 inches and 0.035 inches.

Abstract: A Tri-State circuit element is constructed which is uniquely suited for use in large scale integrated circuit devices wherein a relatively large number of such Tri-State circuits are utilized to drive other circuitry contained within the integrated circuit device. One embodiment of a Tri-State circuit is constructed utilizing a single NAND gate (73), a single inverter (74), a single P channel transistor (76), and two N channel transistors (77, 78) yielding a circuit having a propagation delay of only two gate delays and requiring a total of only nine transistors. Another embodiment of this invention is a Tri-State circuit constructed utilizing a single NOR gate (84), a single inverter (83), a single N channel transistor (88), and two P channel transistors (86, 87). In this embodiment of my invention, a total of nine MOS transistors are required, and the propagation delay between the input terminal and the output terminal is equal to two gate delays.

Abstract: A method for manufacturing a semiconductor integrated circuit device having contact apertures with finely-controlled dimensions of 1 .mu.m or less. An ion bombardment layer is formed by bombarding predetermined portions of the substrate of the semiconductor device with nitrogen ions using a direct ion beam imaging technique. The ion bombardment layer is converted into an oxidation-resistant layer by annealing, and an insulating oxide layer is formed on the surface of the substrate in regions other than those on which the oxidation-resistant layer is formed by oxidation. Thereafter, contact recesses are formed upon removing the oxidation-resistant layer.