Abstract: Disclosed is an electronic device includes a flexible circuit board passing via a first through-hole included in a first housing and a second through-hole included in a second housing, a first support bracket disposed to support the flexible circuit board while covering the first through-hole, a second support bracket disposed to support the flexible circuit board while covering the second through-hole, a first waterproof member disposed to face a partial area of the first through-hole from the first support bracket and inserted into the partial area of the first through-hole, a second waterproof member inserted into the remaining areas of the first through-hole, a third waterproof member disposed to face a partial area of the second through-hole from the second support bracket and inserted into the partial area of the second through-hole, a fourth waterproof member inserted into the remaining areas of the second through-hole.

Abstract: The present invention discloses an automatic signal deployer, a signal deployment system, an automatic signal path deployment method, and a behavior control signal generation method of a deployment agent. The signal deployment system includes an automatic signal deployer, a deployment agent and a base station. The deployment agent receives signal quality data, generates a behavior control signal according to the signal quality data, and sends out the behavior control signal to the automatic signal deployer. The automatic signal deployer receives the behavior control signal and a source signal coming from the base station, performs deployment according to the behavior control signal, whereby the automatic signal deployer can transmit the source signal toward a signal path allocation direction and complete automatic deployment of signal paths.

Abstract: An antenna includes: a dielectric plate provided with a first surface and a second surface; a ground plane located on the first surface; and an antenna unit. A size of the antenna unit is a preset length, the antenna unit includes at least three antenna elements in a ring arrangement, and each antenna element includes a first patch, a second patch, and a third patch that are located on the second surface, and three conductive portions that penetrate through the first surface and the second surface.

Abstract: Disclosed is a pre-5G or 5G communication system for supporting higher data rates beyond 4G communication system such as LTE. An electronic device including a plurality of antenna modules in a wireless communication system is provided. The electronic device includes a transceiver and a processor configured to identify a first RSRP value and a second RSRP value by using a first antenna module of the plurality of antenna modules; determine to monitor a second antenna module of the plurality of antenna modules based on the first RSRP value or the second RSRP value; and, in response to determining to monitor the second antenna module, monitor the second antenna module. The first RSRP value is measured from a first reference signal of a serving cell, and the second RSRP value is measured from a second reference signal of a neighboring cell.

Abstract: An electronic circuit and a method for operating the electronic circuit are provided. The electronic circuit includes a digital filter and a jitter optimization device. The digital filter is configured to receive a first signal and generate a second signal by filtering the first signal. The jitter optimization device is configured to receive the second signal and generate a first parameter and a second parameter according to the second signal. The jitter optimization device is configured to provide a first feature and a second feature associated with the second signal, and the first parameter and the second parameter are generated in response to the first feature or the second feature.

Abstract: A p layer extending in a direction horizontal to a substrate is provided separately from the substrate. An n+ layer and an n layer are provided on respective sides of the layer. A gate insulating layer partially covers the layers. A gate conductor layer partially covers the layer. A gate insulating layer partially covering the layer is provided separately from the layer. A gate conductor layer partially covers the layer. An n+ layer is provided at part of the p layer between the layers. The layers are connected to a bit line, a control line, a word line, a plate line, and a source line, respectively. Memory operation of a dynamic flash memory cell is performed by manipulating voltage of each line.

Abstract: A memory device includes a plurality of pages arrayed in a column direction in a plan view, each page being constituted by a plurality of memory cells arrayed in a row direction on a substrate. Each of the memory cells included in each of the pages includes a semiconductor base material, first and second impurity regions positioned at respective ends of the semiconductor base material, first, second, and third gate conductor layers. The first and second impurity regions, the first, second, and third gate conductor layers are connected to a source line, a bit line, a first select gate line, a plate line, and a second select gate line, respectively. Upon operation end of page write operation and page read operation, voltage of the plate line is set to negative voltage lower than 0 V through capacitive coupling of the plate line and each of the first and second select gate lines to improve data retention characteristics of a write memory cell.

Abstract: A method for forming a 3D memory device is provided. The method comprises forming an array wafer including a core array region, a staircase region, and a periphery region. Forming the array wafer includes forming an alternating dielectric stack on a first substrate, forming a plurality of channel structures in the alternating dielectric stack in the core array region, each channel structure including a functional layer and a channel layer, forming a staircase structure in the staircase region, and forming a plurality of dummy channel structures. The method further comprises bonding a CMOS wafer to the array wafer; and removing the first substrate; removing a portion of functional layer of each channel structure to expose channel layer, and doping the exposed portion of the channel layer.

Abstract: The present disclosure relates to an integrated chip including a first word line and a second word line adjacent to the first word line. The first word line and the second word line both extend along a first direction. A first memory cell is over the first word line and a second memory cell is over the second word line. A first bit line extends over the first memory cell, over the second memory cell, and along a second direction transverse to the first direction. A first dielectric layer is arranged between the first memory cell and the second memory cell. The first dielectric layer extends in a first closed loop to form and enclose a first void within the first dielectric layer. The first void laterally separates the first memory cell from the second memory cell.

Abstract: A method includes recessing a semiconductor fin to form a recess, wherein the semiconductor fin protrudes higher than isolation regions on opposite sides of the semiconductor fin, and performing a first epitaxy to grow a first epitaxy layer extending into the recess. The first epitaxy is performed using a first process gas comprising a silicon-containing gas, silane, and a phosphorous-containing gas. The first epitaxy layer has a first phosphorous atomic percentage. The method further includes performing a second epitaxy to grow a second epitaxy layer extending into the recess and over the first epitaxy layer. The second epitaxy is performed using a second process gas comprising the silicon-containing gas, silane, and the phosphorous-containing gas. The second epitaxy layer has a second phosphorous atomic percentage higher than the first phosphorous atomic percentage.

Abstract: A method of forming a semiconductor device includes: forming an etch stop layer over a substrate; forming a first diffusion barrier layer over the etch stop layer; forming a semiconductor device layer over the first diffusion barrier layer, the semiconductor device layer including a transistor; forming a first interconnect structure over the semiconductor device layer at a front side of the semiconductor device layer, the first interconnect structure electrically coupled to the transistor; attaching the first interconnect structure to a carrier; removing the substrate, the etch stop layer, and the first diffusion barrier layer after the attaching; and forming a second interconnect structure at a backside of the semiconductor device layer after the removing.

Abstract: A device includes a substrate, a first semiconductor fin over the substrate extending in a first lateral direction, a first vertical stack of semiconductor nanosheets over the substrate extending in the first lateral direction, and an inactive fin between the first semiconductor fin and the first vertical stack extending in the first lateral direction. A first gate structure surrounds and covers the first semiconductor fin, and extends in a second lateral direction substantially perpendicular to the first lateral direction. A second gate structure surrounds and covers the first vertical stack, and extends in the second lateral direction.

Abstract: Provided is a semiconductor apparatus comprising: a semiconductor substrate; an element electrode provided above the semiconductor substrate; an element electrode pad electrically connected to the element electrode; and a wire configured to connect to the element electrode pad at a plurality of connection points, wherein the semiconductor substrate includes an emitter region of a first conductivity type arrayed in an array direction, the emitter region facing the element electrode on an upper surface of the semiconductor substrate, wherein a density of the emitter region below a connection point of any of the wires is different from a density of the emitter region below a connection point of any other of the wires.

Abstract: Embodiments of the present disclosure disclose a cross-region document content recognition method, device, apparatus, medium, and program product. A specific implementation of the method includes: performing a document structure recognition processing on an untagged document; for every two adjacent document page numbers in the document page number sequence: selecting a document structure recognition result that corresponds to a first document page number and satisfies a preset tail area condition, as a tail document structure recognition result; selecting a document structure recognition result that corresponds to a second document page number and satisfies a preset head area condition, as a head document structure recognition result; performing a merged detection on the tail document structure recognition result and the head document structure recognition result; in response to the tail document structure recognition result and the head document structure recognition result being mergeable.

Abstract: Embodiments of this application provide an electronic device. The electronic device includes a middle frame, a display, and a fingerprint recognition module. An optical waveguide structure is disposed between the display and the fingerprint recognition module. An optical exit port and at least two optical incident port are formed on the optical waveguide structure. The optical exit port is directly aligned with the fingerprint recognition module. Each optical incident port is directly aligned with a fingerprint recognition area. When a finger touches the fingerprint recognition area to reflect out fingerprint detection light, the fingerprint detection light can be incident into the optical waveguide structure through the optical incident port, and be exported to the fingerprint recognition module through the optical exit port, to implement fingerprint recognition. In this way, there are at least two fingerprint recognition areas of the electronic device.

Abstract: Provided is a valuable medium processing apparatus including: a plurality of devices each of which performs processing related to a transaction of a plurality of kinds of transactions for a plurality of kinds of valuable media; an input device which receives an operation to select a kind of the transaction and at least one of the plurality of kinds of valuable media for the transaction; and a controller which, in a case where an operation to select at least some of the plurality of kinds of valuable media for the transaction are received, operates at least some of the plurality of devices corresponding to the selected at least some of plurality of kinds of valuable media, respectively, in a first mode that causes the at least some of the plurality of devices to start the processing in an order that is predetermined.