Abstract: A protective film containing a transparent polyolefin resin layer with improved or even superior weather resistance, and a sheet using the protective film. A protective film according to the present embodiment includes at least a transparent polyolefin resin layer. The transparent polyolefin resin layer contains a hindered amine light stabilizer represented by general formula (I) below in a range of 0.05 parts by mass or more and 5 parts by mass or less with respect to 100 parts by mass of a transparent olefin resin included in the transparent polyolefin resin layer. (In general formula (I), R is an alkyl group having 1-18 carbon atoms, or a cycloalkyl group having 5-8 carbon atoms.

Abstract: [Object] To reduce the time required to transport a cut sheet and perform printing at a high speed. [Solution] A duplex printer 10 includes a printing unit 12A, a cut sheet feeder 25, and a guide transport path 24. A reversing mechanism 20 that reverses a cut sheet 1 returned from the printing unit 12A is connected to the guide transport path 24 via a switcher 61. A stopper 62 that stops the cut sheet 1 is provided in a part of the guide transport path 24 on the upstream side of the switcher 61. A discharge path 65 branches off from the stopper 62 of the guide transport path 24.

Abstract: A multi-piece connector is provided. The multi-piece connector includes a jumper conductor for electrically interconnecting parts of conductive terminals of the connector, without having to use any additional jumper, such that an electronic device having such a connector can be made more compact in size.

Abstract: A device includes a device layer comprising a first transistor and a second transistor; a first interconnect structure on a front-side of the device layer; and a second interconnect structure on a backside of the device layer. The second interconnect structure comprising a first dielectric layer on the backside of the device layer, wherein a semiconductor material is disposed between the first dielectric layer and a first source/drain region of the first transistor; a contact extending through the first dielectric layer to a second source/drain region of the second transistor; and a first conductive line electrically connected to the second source/drain region of the second transistor through the contact.

Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes a metal gate stack over a substrate and an epitaxial structure over the substrate. The semiconductor device structure also includes a conductive contact electrically connected to the epitaxial structure. A topmost surface of the metal gate stack is vertically disposed between a topmost surface of the conductive contact and a bottommost surface of the conductive contact. The semiconductor device structure further includes a first conductive via electrically connected to the metal gate stack. The topmost surface of the conductive contact is vertically disposed between a topmost surface of the first conductive via and a bottommost surface of the first conductive via. In addition, the semiconductor device structure includes a second conductive via electrically connected to the conductive contact.

Abstract: A semiconductor device includes a first substrate structure including a substrate, circuit elements, and first bonding metal layers, and a second substrate structure connected to the first substrate structure. The second substrate structure includes a plate layer, gate electrodes stacked in a first direction below the plate layer, separation regions penetrating through the gate electrodes and extending in a second direction and spaced apart from each other in the second direction, an insulating region extending from an upper surface of the plate layer and penetrating through the plate layer and at least one of the gate electrodes between the separation regions, and second bonding metal layers connected to the first bonding metal layers. The insulating region has inclined side surfaces such that a width of the insulating region decreases in a direction toward the first substrate structure.

Abstract: A texture recognition pixel circuit includes a photosensitive sub-circuit, a potential raising sub-circuit and a driving output sub-circuit. The photosensitive sub-circuit is configured to, under control of a first voltage transmitted by a first voltage terminal and a potential of the reading node, sense an optical signal including texture information, convert the optical signal into a first detection signal, and transmit the first detection signal to a reading node. The potential raising sub-circuit is configured to, due to an action of a second voltage signal transmitted by a second voltage signal terminal, raise the potential of the reading node. The driving output sub-circuit is configured to, due to an action of the first detection signal that is raised, a third voltage signal transmitted by a third voltage signal terminal and a fourth voltage signal transmitted by a fourth voltage signal terminal, generate and output a second detection signal.

Abstract: In an example operation method of a controller, a mapping relationship of translation from a first physical block address into a first logical block address is written to a first entry according to a write instruction. The first physical block address is a storage address in a memory, and the first logical block address is a storage address recorded in the write instruction. Storage data is written to the first physical block address. A mapping relationship of translation from the first logical block address into the first physical block address is written to a second entry. When a product of first time and second time is greater than or equal to a first value, the second entry is updated into the memory, wherein the first time is theoretical time for refreshing the first entry, and the second time is theoretical time for refreshing the second entry.

Abstract: A wire connection terminal and a welding joint. The novel wire connection terminal includes a terminal substrate (1) provided with a fixing portion for connecting with an electric device and a connecting portion for connecting with a wire (2). The fixing portion is provided with an assembly structure for being assembled with the electric device. The connecting portion is provided with a boss (13) formed by punching the connecting portion for connecting with the wire (2). The wire connection terminal is used for directly welding processing by matching a welding fixture, so as to improve the processing accuracy of the terminal, and avoid brittleness and breakage caused by stress concentration of the terminal.

Abstract: A base station of a communication system may include an antenna; a memory; and a processor. The processor analyzes a signal received through the antenna to determine if the received signal is a signal transmitted from a fake base station. Based on a determination that the source of the received signal is the fake base station, the processor generates a random access preamble signal for accessing the fake base station. The processor transmits the generated random access preamble signal through the antenna. Thus, the base station may effectively defend against an attack from a fake base station by detecting the fake base station based on collected information of a neighboring base station and causing radio resources of the detected fake base station to be exhausted. Various other embodiments are possible.

Abstract: Provided is a semiconductor package having improved signal integrity (SI) and a chip stack structure of a plurality of semiconductor chips. The semiconductor package includes a package substrate, a chip stack structure on the package substrate and including at least two semiconductor chips, and an external connection terminal on a lower surface of the package substrate. A first semiconductor chip arranged uppermost in the chip stack structure is connected to a first bonding pad of the package substrate through a first wire. A second semiconductor chip arranged under the first semiconductor chip in the chip stack structure is connected to a second bonding pad of the package substrate through a second wire. When the first bonding pad is farther from the external connection terminal than the second bonding pad, the external connection terminal is connected to the first bonding pad through a wiring line of the package substrate.

Abstract: An aqua-ozone hygienization system enables hygienization of items through selectable treatment modes: atomized mist for non-wetting deodorization, spray for wetting disinfection, and immersion for purifying, deodorizing, and disinfecting. The system includes a tank with a platform configured to support items and form a water reservoir below. An electrochemical generator produces ozonated concentrate liquid, while a circulating pump delivers the liquid to a switchable nozzle, enabling misting or spraying. The platform may be stationary or retractable, facilitating immersion by accumulating liquid above the platform or lowering items into the reservoir. Egress ports manage liquid flow, ensuring proper drainage post-treatment. Integrated sensors monitor liquid levels and ozone concentration, while a control system automates operations, offering precise treatment customization.

Abstract: The present disclosure provides a polysilicon resistor, a method for manufacturing the same, and a successive approximation register analog-to-digital converter.

Abstract: Embodiments herein disclose methods and systems for managing capabilities of network slice subnets in fifth generation (5G) communication networks. The network slice management function (NSMF) queries the existing network slice subnet's capabilities to determine if the existing network slice subnet can satisfy a network slice requirement. The NSMF receives the capability information of the existing network slice subnet by sending a request to the network slice subnet management function (NSSMF). The capability information of the existing network slice subnet is stored in at least one attribute of an information object class (IOC), wherein the IOC is created by the NSSMF.

Abstract: An example printing device comprises at least one moving module, which includes a profile assembly and a slider assembly. The profile assembly includes two guiding members that are spaced from each other, and the two guiding members respectively have a first guiding groove and a second guiding groove arranged in a preset direction. The slider assembly includes a slider body and an elastic member, where the slider body is in contact with the groove wall of the first guiding groove and is slidably connected in the preset direction; and the elastic member is fixedly connected with the slider body and is in contact with the groove wall of the second guiding groove and is slidably connected in the preset direction. The elastic member can deform to make the slider body press tightly against the corresponding guiding member, so that the printing device can improve its printing quality.

Abstract: The present disclosure provides an array substrate and a display device. The array substrate includes a base substrate and a scan line, a data line, a power supply line, a sensing line, a pixel driving circuit and a light-emitting unit that are sequentially stacked on the base substrate. The array substrate also includes a gate layer, a first conductive layer, a second conductive layer, and a third conductive layer. The first electrode of the storage capacitor is at least disposed at the first conductive layer, and the second electrode of the storage capacitor is at least disposed at the second conductive layer. The data line, the power supply line, and the sensing line are disposed at the third conductive layer.

Abstract: Nanostructure field-effect transistors (NSFETs) including isolation layers formed between epitaxial source/drain regions and semiconductor substrates and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate; a gate stack over the semiconductor substrate, the gate stack including a gate electrode and a gate dielectric layer; a first epitaxial source/drain region adjacent the gate stack; and a high-k dielectric layer extending between the semiconductor substrate and the first epitaxial source/drain region, the high-k dielectric layer contacting the first epitaxial source/drain region, the gate dielectric layer and the high-k dielectric layer including the same material.

Abstract: Disclosed is a storage device, which includes a nonvolatile memory device, and a controller that controls the nonvolatile memory device. In response to a first command, a barrier command, and a second command being received from an external host device, the controller supports an order guarantee between the first command and the second command. Each of the first command and the second command is selected from two or more different commands. In response to a request from the external host device, the controller circuitry is configured to provide the external host device with a device descriptor associated with the ordering.