Abstract: A system, method, and apparatus for distortion analysis is provided. A method in accordance with at least one embodiment of the present disclosure may include receiving a clock frequency at a direct digital synthesizer (DDS) and generating at least one stream of phase numbers via said DDS. The method may further include generating a digital sine wave using, at least in part, said clock frequency and said at least one stream of phase numbers. Of course, additional implementations are also within the scope of the present disclosure.

Abstract: A method, circuit and system for determining at least one of an amplitude and a relative phase of a signal under test. A reference signal is generated based, at least in part, upon the at least one of the amplitude and the relative phase of the signal under test. The reference signal is combined with the signal under test to generate a residual signal indicative of a distortion within the signal under test. The residual signal is measured.

Abstract: A filter includes at least a pin diode, an inductive element, and a varactor diode coupled as a resonant circuit. The filter injects data dependent jitter into a digital data signal with a given data rate for testing a transceiver.

Abstract: The present disclosure relates to a system and method for mapping system transfer functions. Accordingly, some operations may include receiving a first intermediate signal that is at least partially based upon a first reference signal. A second intermediate signal is received that is at least partially based upon a second reference signal. An output signal is generated that is based upon the difference between the first intermediate signal and the second intermediate signal. A first anticipated differential change in the output signal is determined, the first anticipated differential change to occur based upon a transition in the first reference signal. A second anticipated differential change in the output signal is determined, the second anticipated differential change to occur based upon a transition in the second reference signal. Numerous other operations are also within the scope of the present disclosure.

Abstract: A method is described for facilitating use of a first pattern utilizing XOR data formatting in an electronic tester. The method includes dividing the first pattern into at least a first group and a second group, the tester to successively execute the first group and the second group. The method further includes assuming an entry state for each group is one of two binary conditions and inverting programmed commands for the second group if an ending state of the first group is not equal to the assumed entry state.

Abstract: A method, circuit and system for determining at least one of an amplitude and a relative phase of a signal under test. A reference signal is generated based, at least in part, upon the at least one of the amplitude and the relative phase of the signal under test. The reference signal is combined with the signal under test to generate a residual signal indicative of a distortion within the signal under test. The residual signal is measured.

Abstract: A digital tester includes a digital data pattern aligner. The digital data pattern aligner includes an alignment pattern source, a data shifter, and a data comparator. The alignment pattern source sends an alignment pattern to the comparator in a data stream. The comparator samples the data stream and compares the samples to a copy of the alignment pattern. The shifter shifts the data in the data stream so long as the comparator detects no match between a data stream sample and the copy of the alignment pattern. When a match is detected, the pattern source and the comparator are in alignment and other data, such as test patterns, may be sent to the comparator or associated components.

Abstract: A variable attenuation device includes a resistive array having two or more input nodes, two or more output nodes, and two or more resistive devices for coupling the input nodes and the output nodes. A first switch has an input terminal and two or more selectable output terminals, such that the input terminal is configured to receive an input signal and the two or more selectable output terminals are coupled to the two or more input nodes of the resistive array. A second switch has two or more selectable input terminals and an output terminal, such that the output terminal is configured to provide an attenuated output signal and the two or more selectable input terminals are coupled to the two or more output nodes of the resistive array.

Abstract: An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patterns to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns.

Abstract: An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patterns to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns.

Abstract: A data shifter selects data from a plurality of data blocks to effectively “window” data contained within the blocks. A second stage of shifting may be implemented by selection among the resultants of the windowing step. Such a shifter may find use in a data aligner.

Abstract: A circuit board cooling system employs a closed liquid delivery system to transfer heat from integrated circuits to a cooling liquid. The system includes one or more cooling panels that may be attached to a circuit board. Each cooing panel includes at least one channel for the circulation of cooling liquid stamped into a thermally conductive material. Each panel may include multiple levels in order to conform to the profile of integrated circuits to be cooled.

Abstract: A method and apparatus for a micromachine relay is provided. A pin controller comprises at least one spring pin designed to movably couple the pin controller to a device under test (DUT) to provide signals to the DUT. The pin controller further includes a micromachine relay coupled to the at least one spring pin to control the movement of the at least one spring pin and an integrated circuit for controlling the micromachine relay.

Abstract: A method of connecting one or more testing devices to ports of a DUT through a switching network, to execute a testing procedure includes generating a switching network map defining connections within the switching network to implement electrical paths through the switching network. Each of the electrical paths is representative of a connection of one of the testing devices to one of the I/O ports of the DUT. The method further includes receiving commands that uniquely specify an electrical path connecting a particular testing device to a particular I/O port of the DUT. The method compares each command to the switching network map to identify a corresponding electrical path through the switching network, and implements that path associated the command through the network. The method further includes sequentially implementing the electrical paths corresponding to the one or more commands in a predetermined order.

Abstract: A phase-locked loop circuit having a programmable tuning voltage. As the input reference clock frequency is changed, the tuning voltage is changed accordingly to compensate for the propagation delay through the phase detector and thereby reduce discrepancies in the phase relationship between the input reference clock signal and the output clock signal at different frequencies. A set of compensation values corresponding to input reference clock frequencies are stored in a memory device. When the input reference clock frequency is changed, a corresponding compensation value is programmed to a digital-to-analog converter (DAC). The DAC outputs a voltage that is proportional to the value of the digital input to the DAC and can thus be used to regulate the tuning voltage of the PLL circuit so that the relationship of the input reference clock signal to the output clock signal remains stable with frequency changes.

Abstract: An apparatus to receive a response signal sent from a device under test. The apparatus includes pin electronics to identify a response signal contained in a composite signal. The composite signal is a composite, or sum, of the response signal and a test signal. The pin electronics has a driver to send the test signal to the device under test, and a receiver to receive the composite signal and to separate the response signal from the composite signal.

Abstract: A method and apparatus for a micromachine relay is provided. A pin controller comprises at least one spring pin designed to movably couple the pin controller to a device under test (DUT) to provide signals to the DUT. The pin controller further includes a micromachine relay coupled to the at least one spring pin to control the movement of the at least one spring pin and an integrated circuit for controlling the micromachine relay.

Abstract: An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patters to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns.

Abstract: A circuit board cooler employs a closed fluid delivery system to transfer heat from electronic components to a cooling fluid. One or more channels embedded within the circuit board carry cooling fluid to the components where the fluid absorbs heat from the component, then away from the component to deposit the excess thermal energy in a thermal sink, such as a heat exchanger. The cooling system may employ conductive thermal transfer elements, such as “thermal vias”, to enhance heat transfer from electronic components to the cooling fluid.

Abstract: A mixed signal integrated circuit testing system includes a system controller connected to a test head for controlling the testing operations of the mixed signal integrated circuit testing system. The test head is adapted to support a wide combination of both the analog and digital circuit testing modules. A DUT board, typically configured for a specific IC or family of ICs, is used to connect the circuit testing modules to the IC. The DUT board is connected to a DUT board interface that includes an analog DUT board interface adapter and a digital DUT board interface adapter. The digital DUT board interface adapter is connected directly to the digital circuit testing modules. The analog DUT board interface adapter is connected to a system configuration module that provides analog loading and conditioning circuitry as well as other circuitry that can be customized for testing specific ICs.