Abstract: An apparatus to receive a response signal sent from a device under test. The apparatus includes pin electronics to identify a response signal contained in a composite signal. The composite signal is a composite, or sum, of the response signal and a test signal. The pin electronics has a driver to send the test signal to the device under test, and a receiver to receive the composite signal and to separate the response signal from the composite signal.

Abstract: A method is described that decompresses at least a section of a first test pattern within a first decompression engine while simultaneously decompressing at least a section of a second test pattern within a second decompression engine. The first test pattern is to be applied to a first device under test (DUT) connection. The second test pattern is to be applied to a second DUT connection.

Abstract: An automated test system that has analog and digital resources for testing mixed signal ICs. A control pattern is provided that is used by the automated test system to simultaneously control both the digital resources and the analog resources. The control pattern is comprised of a sequentially executed two-dimensional array with columns corresponding to analog and digital resources. The automated test system uses the control pattern to control both the analog and digital resources.

Abstract: A test system for testing at least one electrical component includes a test head having a mounting assembly for removably attaching the electrical component, and a plurality of test ports for electrically coupling to the electrical component. The test system further includes a voltage and current source located within the test head. The voltage and current source is constructed and arranged so as to provide at least one electrical output, through an interface assembly, to the electrical component. The electrical output has a voltage magnitude within a predetermined voltage range and has a current magnitude within a predetermined current range. The voltage and current source further analyzes the electrical output so as to detect and measure one or more changes to the electrical output caused by the electrical component. The voltage and current source also receives and analyzes a plurality of response signals through the interface assembly from the signal ports of the electrical component.

Abstract: An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patterns to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns.

Abstract: A method of generating a plot that evinces common result regions of a test as a function of controllable input parameters includes defining an overall plot region that is a function of the maximum and a minimum of each input parameter. The method further subdivides the overall plot region into at least two sub-regions, where each of the sub-regions has a sub-region boundary. The method evaluates, for each of the sub-regions, a plurality of boundary test conditions on the sub-region boundary according to the test, so as to assign a test status to each of the plurality of boundary test conditions. For each of the sub-regions with at least a predetermined threshold number of boundary test conditions having a common test status, the method designates the sub-region with the common test status. For each of the sub-regions not having at least the predetermined threshold number of boundary test conditions with a common test status, the method designates that sub-region with an indeterminate status.

Abstract: A software tool for analyzing the real-time performance characteristics of computer programs. A subprogram automatically records the execution time at a large number of pre-identified points in the code to be analyzed. This time information is captured in real-time and is minimally invasive. The display is subsequently displayed using a timing diagram display tool for a graphical user interface. The displayed timing diagrams provides a visual representation of the execution of the software in time, and provides a user to scale the time or show the profile in an alternate perspective. The present invention further provides a graphical representation of the hierarchical execution of subroutines and program modules within the software by displaying the nested execution of the software.

Abstract: A test circuit operable to examine both differential outputs and single outputs of a device under test (DUT), the circuit comprises a first circuit having as inputs a first output of the DUT and a first set of independent reference voltages, and an output of the first circuit coupled to a plurality of comparators. The test circuit further comprises a second circuit having as inputs a second output of the DUT and a second set of independent reference voltages, and an output of the second circuit coupled to the plurality of comparators. The test circuit further comprises a select circuit coupled to outputs of the comparators, the output of the first circuit and the output of the second circuit. The select circuit outputting the outputs of the first circuit and the second circuit or outputting the outputs of the comparators.

Abstract: A programmable load circuit operable to generate a plurality of test signals is described. The programmable load circuit comprises a diode bridge coupled between an input and an output. The diode bridge compares the voltage on the input to the voltage on the output. The programmable load circuit also comprises a plurality of current sources. A first set of the plurality of current sources are coupled to intermediate nodes of the diode bridge. Additionally, the programmable load circuit comprises a switching circuit coupled between the intermediate nodes of the diode bridge and a second set of the plurality of current sources. Furthermore, the programmable load circuit also comprises a load regulator coupled to the output and the intermediate nodes of the diode bridge. The load regulator is configured to reduce leakage current on the output.

Abstract: A tester circuit generating differential signals, single ended signals, or a fast transitioning signal to exercise inputs of a device under test is described. According to one embodiment, the tester circuit includes a first circuit configured to generate a first test signal on an input of the first driver. The tester circuit also includes a second circuit configured to generate a second test signal on an input of a second driver. Further, the tester circuit also includes select signals and select logic to determine the different testing modes of the device under test.

Abstract: A load counterbalancing system with a constant load displacement force includes a load element, a position transducer and an actuator element. An environmental force acting upon the load element is counterbalanced by a support force provided by the actuator element. The environmental force is assumed to be a predetermined function of the position of the load element, and the actuator element applies the support force to the load element as defined by the predetermined function. The invention allows an operator to move the load element through its entire range of motion with a constant applied force, and to place the load element statically at any position in the range of motion.

Abstract: A local trigger signal generator is provided for each of a plurality of test instruments in a test system. The disclosed test system includes a master clock generator that defines a start time t.sub.0 and generates a periodic master clock signal characterized by a master clock oscillation frequency f.sub.mc and a corresponding period T.sub.mc. The master clock generator generates a clock network signal that is representative of the master clock signal and the start time t.sub.0. The system further includes a set of n test instruments TIN1, TIN2, . . . TINn. An ith one of the test instruments TINi includes a local clock receiver for receiving the clock network signal and defining therefrom a local start time t.sub.0 i and for generating therefrom a local timestamp signal LTSSi, where the local timestamp signal LTSSi is representative of a number of time intervals having a length substantially equal to the period T.sub.mc occurring after the local start time t.sub.0 i.

Abstract: A process for determining a quiescent power supply current (I.sub.DDQ) of a device under test (DUT) at a first node. The process includes the steps of providing a reference current to the first node and decoupling a power supply from the first node. A first node voltage is determined at a first time after the power supply is decoupled from the first node. The first node voltage is determined at a second time after the first time. If the first node voltage increases from the first time to the second time, it is indicated that the I.sub.DDQ of the DUT is less than the reference current. If the first node voltage decreases from the first time to the second time, it is indicated that the I.sub.DDQ of the DUT is greater than the reference current.

Abstract: The disclosed apparatus includes first and second delay lines, the first delay line having an input tap and a set of n output taps F.sub.1, F.sub.2, . . . F.sub.n, and the second delay line having an input tap and a set of n output taps S.sub.1, S.sub.2, . . . S.sub.n, and each of the output taps has an associated delay interval. A first signal representative of a first event is applied to the input tap of the first delay line, and a second signal representative of a second event is applied to the input tap of the second delay line. The disclosed apparatus further includes a set of n latches L.sub.1, L.sub.2, . . . L.sub.n, and a set of n delay units D.sub.1, D.sub.2, . . . D.sub.n. The output signals generated by taps F.sub.i and S.sub.i are applied to a first input terminal and a second input terminal, respectively, of latch L.sub.i.

Abstract: A process for determining a quiescent power supply current (I.sub.DDQ) of a device under test (DUT) at a first node. The process includes the steps of providing a reference current to the first node and decoupling a power supply from the first node. A first node voltage is determined at a first time after the power supply is decoupled from the first node. The first node voltage is determined at a second time after the first time. If the first node voltage increases from the first time to the second time, it is indicated that the I.sub.DDQ of the DUT is less than the reference current. If the first node voltage decreases from the first time to the second time, it is indicated that the I.sub.DDQ of the DUT is greater than the reference current.

Abstract: A method and apparatus for generating timing markers in an automatic electrical test system. Timing parameters are synchronized by an external period start signal corresponding to a centrally generated external period and an internal period start signal generated locally for each input/output pin. The timing parameters comprise T1 counter and vernier values, T2 counter and vernier values, and period-minus-T1 counter and period vernier values.

Abstract: An apparatus for a test system for testing an electronic circuit. The apparatus includes an interconnect path, a comparator, a programmable apparatus, a first Schottky diode, and a second Schottky diode. The interconnect path has a first end and a second end. The first end of the interconnect path is coupled to the electronic circuit under test. The interconnect path transmits a signal from the electronic circuit under test to the second end of the interconnect path. The comparator is coupled to the second end of the interconnect path for receiving and comparing the signal from the electronic circuit under test with a reference voltage. The comparator has a high input impedance. The comparator provides an output signal to the test system. The programmable apparatus provides a selectable first voltage and a selectable second voltage. A first Schottky diode is provided for reducing ringing of the signal from the electronic circuit under test.

Abstract: A phase shift vernier for providing an output signal with continuously variable delay based on an input phase delay is disclosed. The apparatus comprises delay value means, a ring oscillator, a multiplexer, a DAC, and a signal combiner. The delay value means is adapted for receiving an input phase delay value, indicating the amount of delay for an output signal. The ring oscillator is adapted for circulating an oscillating signal through multiple differential stages to generate multiple quadrature signals. The oscillating signal has a predetermined frequency and each of the differential stages is connected in series. Each of the stages delays its inputs by a predetermined amount to generate its differential outputs from each stage. The multiplexor is coupled to the ring oscillator and to the delay value means to receive the quadrature signals from the ring oscillator.