Abstract: A logic circuit is simulated for mapping and emulation on a field programmable gate array-based platform by mapping one or more of the circuit delays onto delay elements in the FPGA-based platform. The operations of the delay elements are controlled by one or more simulations clocks that are different from any user-specified clocks.

Abstract: An integrated circuit, a contact and a method of manufacture therefor. The integrated circuit has a silicon substrate with a recess formed therein that provides an environment within which the contact is formed. The contact includes: (1) an adhesion layer deposited on an inner surface of the recess, (2) an amorphous layer, deposited over the adhesion layer within the recess and (3) a central plug, composed of a conductive material, deposited at least partially within the recess, the silicide layer being amorphous to prevent the conductive material from passing through the amorphous silicide layer to contact the adhesion layer thereby to prevent junction leakage.

Abstract: The called party can temporarily defer answering a call simply by pressing a button on the station set. When the button is pressed, the called party's station set sends a data message to the system's voice response unit directing the voice response to play a "please wait" message to the calling party rather than sending the calling party to the called party's voice mail. The voice response unit plays the "please wait" message to the calling party and sends a call park message to the switching system hosting the station set. The call park message to the switching system directs the switching system to park the call at a specific location as is known in the art and a corresponding call park message to the station set transmits the location of the parked call to the station set. When the called party desires to answer the call, a message is sent from the station set to the switching system requesting that the call parked at the identified location be connected to the station set.

Abstract: Any existing transitive closure in a database can be found using a method based on standard 4th Generation Structured Query Language (SQL) without non-standard extensions to perform recursion analysis. Once a transitive closure table is compiled, SQL and the transitive closure table can be used to calculate critical path lengths, sums, averages, or other values, through a directed acyclical graph. Since this method uses instructions that are entirely within standard 4GL SQL, it can be used over multiple platforms as long as the platforms are 4GL SQL compliant.

Abstract: A face feature analysis which begins by generating multiple face feature candidates, e.g., eyes and nose positions, using an isolated frame face analysis. Then, a nostril tracking window is defined around a nose candidate and tests are applied to the pixels therein based on percentages of skin color area pixels and nostril area pixels to determine whether the nose candidate represents an actual nose. Once actual nostrils are identified, size, separation and contiguity of the actual nostrils is determined by projecting the nostril pixels within the nostril tracking window. A mouth window is defined around the mouth region and mouth detail analysis is then applied to the pixels within the mouth window to identify inner mouth and teeth pixels and therefrom generate an inner mouth contour. The nostril position and inner mouth contour are used to generate a synthetic model head.

Abstract: A multi-stage mixer circuit has two or more mixer stages, each stage having a mixer core and successive mixer cores being separated by one or more current mirrors. By using current mirrors to process the currents generated by the mixer cores, instead of current-to-voltage and voltage-to-current converters as in the prior art, the present invention provides a mixer circuit with reduced signal distortion and power dissipation. In one embodiment, the two mixer cores of a two-stage mixer circuit are implemented using the same type of transistor devices (e.g., N-type), and there are two current mirrors between the mixer cores. In another embodiment, the two mixer cores of a two-stage mixer circuit are implemented using different types of transistor devices (i.e., one N-type and the other P-type), and there is only one current mirror between the mixer cores.

Abstract: An electronic assembly having a first component, a second component, and a layer of adhesive bonding the first and second components together, one or both of the first and second components includes thinned or tapered peripheral edges. The layer of adhesive includes a thickened portion which is adjacent to the thinned or tapered peripheral edges, the thickened portion having a thickness which is greater than the thickness of the remaining portion of the layer.

Abstract: Apparatus and method for retaining a laser bar during a facet coating operation and releasing the laser bar subsequent to the operation. The apparatus includes a pair of opposing spacers that hold the laser bar when compressed, each spacer including a compliant spring on an inner portion thereof. A compression device applies a force to the spacers sufficient to compress the springs against opposite sides of the laser bar to thereby retain the laser bar during the facet coating operation. Subsequent to the facet coating operation, the compressive force is released to decompress the springs and thereby release the laser bar. Due to the spring action, the laser bar is released without substantially adhering to either one of the spacers.

Abstract: The audible noise suppressor for planar magnetic devices functions to eliminate the audible noise generated by the normal operation of a planar magnetic device. This is accomplished by the use of a spacer device which functions to fill the gap between the ferrite core and the printed wiring board. The planar magnetic device comprises an E-shaped ferrite core comprising first second and middle legs, the three legs being inserted through mating holes formed in the printed wiring board. The windings of the planar magnetic device are deposited on the surface of the printed wiring board, in a predetermined pattern about the middle leg of the E-shaped ferrite core that protrudes through the corresponding hole in the printed wiring board. An I-shaped ferrite core is placed in position to span the first, second and middle legs of the E-shaped ferrite core. The E-shaped and I-shaped ferrite cores are held in place by the use of a clip that snap fits over the two ferrite cores.

Abstract: A process for fabricating a vertical MOSFET device for use in integrated circuits is disclosed. In the process, at least three layers of material are formed sequentially on a semiconductor substrate. The three layers are arranged such that the second layer is interposed between the first and third layers. The second layer is sacrificial, that is, the layer is completely removed during subsequent processing. The thickness of the second layer defines the physical gate length of the vertical MOSFET. In the process the first and third layers have etch rates that are significantly lower than the etch rate of the second layer in an etchant selected to remove the second layer.After the at least three layers of material are formed on the substrate, a window or trench is formed in the layers. The window terminates at the surface of the silicon substrate in which one of either a source or drain region is formed in the silicon substrate. The window or trench is then filled with a semiconductor material.

Abstract: In accordance with the present invention, a wavelength selectable laser source comprises a tunable pump source, an array of waveguide lasers for emitting light at respectively different wavelengths and a router for directing light from the pump source to an appropriate waveguide laser. A second router can be used to direct all laser outputs to a common output waveguide. The result is a wavelength selectable, stable signal source. In preferred embodiments the routers are dense wavelength-division multiplexers (DWDMs) and the waveguide lasers are rare-earth doped fiber lasers. Alternative embodiments provide a variety of ways of routing the pumping source.

Abstract: Providing a common broadcast channel in a WDM (wavelength division multiplexed) system is accomplished by applying a pulsed light source to a dispersive delay line, and also applying the light source to each of M delay lines, such that the Mth delay line has a delay of (M-1) time slots, where M is a nonnegative integer representing the number of time slots to be provided for the broadcast channel. The dispersive delay line spreads the spectrum of the pulsed light source across the desired bandwidth of the WDM system to provide a wide-spectrum signal, and this wide-spectrum signal may then be modulated to provide a plurality of WDM channels. The M delay lines provide delayed pulses that may be modulated to provide a common broadcast channel for reception on a plurality of WDM receivers.

Abstract: An assembly for mounting terminal array connectors to a surface. The assembly includes a generally planar bracket having a first surface and a second surface. A plurality of apertures are formed through the bracket, wherein the apertures include wire apertures, screw apertures and anchor apertures. One or two wire connectors are affixed to the bracket, wherein each side of the bracket is capable of supporting one wire connector. At least one spacer is disposed between the bracket and each wire connector that it supports. The spacers prevent each wire connector from contacting bracket and shorting against the material of the bracket. The wire connectors and spacers are affixed to the bracket by at least one mechanical fastener. The mechanical fasteners extend through the screw apertures in the bracket and the spacers, wherein the mechanical fasteners engage the body of the wire connector being mounted.

Abstract: A pipelined Fast Hadamard Transform ("FHT") architecture is disclosed that comprises log.sub.2 N identical pipeline stages, which are ideally suited for implementation in application-specific integrated circuits. One 2-port stage of the first illustrative embodiment of the present invention advantageously comprises: a first input for sequentially receiving N incoming correlation signals, I(i), at cycle i, wherein the N incoming correlation signals are based on N Walsh chips; a processor for generating N outgoing correlation signals based on the N incoming correlation signals, I(i); and a first output for sequentially outputting the N outgoing correlation signals, O(i); wherein ##EQU1## k=(i-N/2).

Abstract: The specification relates to the encryption of data transmitted over a broadband multiple access bi-directional hybrid fiber/coax (HFC) network. The method supports downstream broadcast encryption from headend to cable modem, and also provides for encryption of transmissions from cable modems back to the headend. Although the present invention is described in relation to an HFC network, it is also equally applicable to a cellular wireless communications environment or any other digital broadcast medium. The invention is implemented in two subdivisions, a slow but secure software encrypting algorithm, and a fast but less secure hardware encrypting algorithm. The combination produces the security of the software subdivision, with the encrypting speed of the hardware subdivision. The encryption method and apparatus supports the various access and transmission modes, such as STM, ATM, and VL.

Abstract: A low cost radio frequency identification tag is provided for attaching to and identifying objects such as, for example, a passenger's luggage. The tag is programmed to contain information such as the origin, destination, and name of a passenger accompanying the luggage. This information is programmed into the tag at the time when the customer checks his or her luggage at a terminal. The tag includes an integrated circuit with all radio and data functions incorporated onto this integrated circuit, and an antenna for radio communication. The integrated circuit in the tag is suitably powered from the incident radio frequency energy provided by a interrogator while the tag is located in the radiation pattern of this interrogator. The luggage tag is assembled inexpensively by packaging the integrated circuit between paper or plastic substrates on which printed identifying information is also added at the point of check-in at the terminal.

Abstract: A field-programmable gate array (FPGA) having at least one programmable cell (e.g., an input/output (I/O) cell) having an output node circuit (e.g., a pad circuit) in which the output data signal and the tri-state signal are applied to a multiplexer that drives the tri-state port of an output buffer in the output node circuit. This configuration enables the output node circuit to be configured for open drain drive mode operations in a fast, predictable manner that does not need to rely on the FPGA's general routing resources.

Abstract: A hingeable leg subassembly for a wiring block of the type having a wiring base includes a wiring base support and a foot spaced away from the wiring base support along the leg. The foot has a lower surface and a generally opposite upper surface which defines an aperture therethrough. The aperture has an entrance at the upper surface, having a first size which is less than a second size at an exit on the lower surface. A wiring block is formed with two of the hingeable leg subassemblies, with a wiring base affixed to the hingeable leg subassemblies and a wiring strip supported by the wiring base is also disclosed.

Abstract: An IC includes a clamp transistor for limiting the voltage at a circuit node and a current amplifier coupled across the input and output terminals of the clamp transistor. In one embodiment the current amplifier comprises a current mirror. In a differential line driver, the direction of current through a load is controlled by means of pair of dual-function transistors which also serve to provide current gain in separate current mirrors.

Abstract: A system which utilizes a control interface of a powered component of a device to protect said component from being corrupted by random values which may be present on the control interface as a result of powering off or powering on an attached device component. When the powered component powers off the attached component, the powered component is locked and ignores any control sequences from the attached component until the attached component is powered back on and the attached component sends a correct unlock sequence to the control interface to unlock the powered component.