Patents Assigned to MACOM CONNECTIVITY SOLUTIONS, LLC
  • Patent number: 10637780
    Abstract: Systems and methods for multi-channel signal processing by virtue of packet-based time-slicing with single processing core logic. The processing core logic is configured to receive data streams from the multiple communication channels at a data processing unit, and process data fragments of the data streams in a time-sliced manner. The processing core logic can switch from processing a first data fragment of a first data stream to processing a first data fragment of a second data stream at an end of a time slice, wherein the time slice is determined by a fragment boundary associated with the data fragment of the first data stream.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: April 28, 2020
    Assignee: MACOM Connectivity Solutions, LLC
    Inventor: Dimitri Mavroidis
  • Patent number: 10455501
    Abstract: System and method of frame alignment at a receiver with power optimization mechanisms. A framer at the receiver is configured to process data streams from multiple physical lanes and/or multiple channels serially. The receiver may include multiple framers that process different sets of data streams in parallel. A framer may enter a power reduction mode after all the channels associated therewith have achieved frame alignment. The framer can be restarted to perform frame alignment processes on a particular channel responsive to an indication that the channel transitions to an out-of-frame state. The “out-of-frame” indication may be generated by a forward error correction (FEC) decoder when it detects an excessive number of uncorrectable errors in the channel.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: October 22, 2019
    Assignee: MACOM Connectivity Solutions, LLC
    Inventors: Francesco Caggioni, Dimitrios Giannakopoulos
  • Patent number: 10313102
    Abstract: System and method of frame alignment at a receiver with power optimization mechanisms. A framer is configured to perform a frame alignment process on a data stream and enter an inactive state after frame alignment is achieved. In the inactive state, the circuits used to perform the frame alignment process in the framer can be powered down or otherwise placed in a power reduction mode. Responsive to an indication that data processing at the receiver becomes “out-of-frame” again, the framer can wake up from the inactive state and restart the frame alignment process. An “out-of-frame” indication may be generated by error detection logic (e.g., forward error correction (FEC) decoder) when it detects an excessive number of uncorrectable errors.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: June 4, 2019
    Assignee: MACOM Connectivity Solutions, LLC
    Inventors: Francesco Caggioni, Dimitrios Giannakopoulos
  • Patent number: 10243762
    Abstract: An analog-based architecture is used to produce tap spacings in an n-tap fractionally-spaced equalizer without the need for digital clock-driven elements. The analog voltage-controlled delay cell circuits control the amount of applied delay based on the measured phase difference between quarter-rate clock signals. Because low speed clock signals are sufficient for comparison purposes, the analog delay cells can be placed before the quarter-rate multiplexors in the data path. The use of analog-based delay cells eliminates the need to route high-speed clock signals to multiple digital delay elements that are typically used to achieve fractionally spaced data signals in n-tap FIR equalizers. Timing margin issues can also be eliminated since digital clocked elements are not used to produce the fractionally spaced delays. The analog-based delay approach also consumes less power relative equalizers that use multiple digital delay elements requiring high speed clock signals.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: March 26, 2019
    Assignee: MACOM CONNECTIVITY SOLUTIONS, LLC
    Inventors: Aniket Kadkol, Mahmoud Reza Ahmadi, Echere Iroaga
  • Patent number: 10142091
    Abstract: System and method of frame alignment at a receiver with power optimization mechanisms. A framer uses one or more comparators to search for the FAW in the incoming data, with each comparator configured to serially compare multiple windows of a parallel M-bit block (as provided from a parallel data bus) with the FAW. Multiple comparators in the framer may operate in parallel to search for the FAW at different windows. This configuration can significantly reduce the comparator count and so the gate count as well as the chip area in a framer. Power consumption can be advantageously reduced as one comparator operating serially consumes less power than multiple comparators in parallel because less gate toggling is involved.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: November 27, 2018
    Assignee: MACOM CONNECTIVITY SOLUTIONS, LLC
    Inventors: Francesco Caggioni, Dimitrios Giannakopoulos
  • Patent number: 10135606
    Abstract: System and method of timing recovery for recovering a clock signal with reduced interference with clock phase correction by an adaptive equalizer. The equalizer in the timing recovery loop is dynamically adapted to the current channel characteristics that vary over time. The equalizer includes compensation logic operable to detect and compensate a correction of clock phase ascribed to the equalization adaptation. The compensation logic can calculate the offset between a center of filter (COF) value and a COF nominal value, the offset indicative of the amount and direction of clock phase correction contributed by the equalizer. Based on the offset, the compensation logic adjusts the equalized signal by adjusting the tap weights of the equalizer to correct the offset, thereby compensating the clock phase correction.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: November 20, 2018
    Assignee: MACOM Connectivity Solutions, LLC
    Inventors: Yehuda Azenkot, Bart R. Zeydel
  • Patent number: 10110334
    Abstract: Techniques efficiently serialize multiple data streams using quadrature clocks. Serializer employs first, second, third, and fourth clock signals. Serializer receives multiple data streams via registers, with each of four paths comprising a register, buffer, and switch, with registers of first and fourth paths associated with third clock signal, and registers of second and third paths associated with first clock signal, and with switches of first and fourth paths associated with first clock signal, and switches of second and third paths associated with third clock signal. Switches of first and second paths transfer respective data bits to fifth switch via another buffer, wherein fifth switch is associated with a delayed second clock signal of a time delay component (TDC). Switches of third and fourth paths transfer respective data bits to sixth switch via another buffer, wherein sixth switch is associated with a delayed fourth clock signal of TDC.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: October 23, 2018
    Assignee: MACOM CONNECTIVITY SOLUTIONS, LLC
    Inventors: Vijay Gupta, Tarun Gupta
  • Patent number: 10014876
    Abstract: System and method of buffering sampled signals in a time-interleaved analog-to-digital converter (ADC). When the input voltage to the buffer varies to a different level, a constant reset voltage is supplied to the buffer output that drives a large capacitive load, e.g., composed of an array of sub-ADCs. The reset voltage functions to remove the capacitive effect from a previous output value on the load. As a result, the buffer can buffer the input for the load without introducing intersymbol interference (ISI). A reset switch can be used to control the supply of the reset voltage to the buffer output according to a predetermined clock signal. The reset voltage may be the common mode potential in a differential source follower in the buffer. An additional voltage gain can be advantageously achieved by the buffer with a gain factor being independent of the load capacitance.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: July 3, 2018
    Assignee: MACOM Connectivity Solutions, LLC
    Inventor: Nanda Govind Jayaraman
  • Patent number: 9991907
    Abstract: A transceiver architectures can contain an encoder and a decoder for communicating high speed transmissions. The encoder can modulate signal data for being mapped in a constellation that is generated based on concatenations of an E8 lattice having binary and non-binary codes. The data can be transmitted at a high speed according to the constellation with an embedded E8 lattice configuration in order to generate a coding gain. A decoder operates to decode the received input signal data with a decreased latency or a minimal latency with a high spectral efficiency.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: June 5, 2018
    Assignee: MACOM CONNECTIVITY SOLUTIONS, LLC
    Inventor: Dariush Dabiri
  • Patent number: 9973203
    Abstract: An interleaved DAC utilizes a set of positive sub-DACs and a set of negative sub-DACs for converting digital inputs in parallel without return to zero. For each digital input, a positive sub-DAC performs conversion and drives its analog output for a duration of N/fs; and a negative sub-DAC performs conversion and drives its analog output for a duration of (N?1)/fs; and by a delay of 1/fs. By combining the outputs from the two sets of sub-DACs, the output from the positive sub-DAC is effectively removed when it is no longer needed at the combined output. As a result, the combined analog signal has each data point valid only for a duration of T, thereby achieving the desired data conversion speed of fs.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: May 15, 2018
    Assignee: MACOM Connectivity Solutions, LLC.
    Inventors: Yehuda Azenkot, Nanda Govind Jayamaran
  • Patent number: 9954547
    Abstract: An interleaved DAC configured to generate a set of second digital inputs responsive to a set of first digital inputs. Each second digital input is obtained by subtracting the other second digital inputs in the set from the corresponding first digital input. Two consecutive first digital inputs are shifted by a phase of T=1/fs. The second digital inputs are supplied to a set of sub-DACs arrange in parallel. Each sub-DAC operates at a frequency of fs/R, and drives an analog output responsive to each second digital input for a duration of R×T. Clock signals used by two sub-DACs for converting two consecutive second digital inputs are offset by a phase of T. In each interval of T, summation of the analog signals output from the set of sub-DACs produces an analog value of a single first digital input, thereby achieving a data conversion speed of fs.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: April 24, 2018
    Assignee: MACOM Connectivity Solutions, LLC
    Inventors: Yehuda Azenkot, Nanda Govind Jayaraman
  • Patent number: 9948427
    Abstract: System and method of comparing-selecting state metric values for high speed Viterbi decoding. In an Add-Compare-Select (ACS) unit, a select control signal is produced by Boolean operations on comparator decision signals and used to control a multiplexer structure. The comparator decision signals can be generated in parallel by an array of comparators comparing all possible pairs of a set of state metrics values. The Boolean operations are predefined through Boolean algebra that uses the decision signals as variables and complies with restriction imposed by the selection criteria, e.g., to select an minimum or maximum value of the set of state metrics values. The Boolean operations are performed by a logic module implemented using basic logic gates, such as AND, OR and NOT. As a result, the multiplexer structure that receives the set of input values can output the optimum value responsive to the select control signal.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: April 17, 2018
    Assignee: MACOM Connectivity Solutions, LLC
    Inventors: Yehuda Azenkot, Bart Zeydel
  • Patent number: 9893999
    Abstract: Systems and methods for multi-channel signal processing by virtue of packet-based time-slicing with single processing core logic. The processing core logic is configured to receive data streams from the multiple communication channels at a data processing unit, and process data fragments of the data streams in a time-sliced manner. The processing core logic can switch from processing a first data fragment of a first data stream to processing a first data fragment of a second data stream at an end of a time slice, wherein the time slice is determined by a fragment boundary associated with the data fragment of the first data stream.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: February 13, 2018
    Assignee: MACOM Connectivity Solutions, LLC
    Inventor: Dimitri Mavroidis
  • Patent number: 9880849
    Abstract: Various aspects provide for detecting ordering violations in a memory system. A system includes a prediction component and an execution component. The prediction component predicts whether a load instruction in the system is associated with an instruction pipeline hazard. The execution component allocates the load instruction to a queue buffer in the system in response to a prediction that the load instruction is not associated with the instruction pipeline hazard.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: January 30, 2018
    Assignee: MACOM CONNECTIVITY SOLUTIONS, LLC
    Inventors: Matthew Ashcraft, Richard W. Thaik
  • Patent number: 9882709
    Abstract: System and method of timing recovery for recovering a clock signal by using adaptive channel response estimation. The channel response estimation in the timing recovery loop is dynamically adapted to the current channel response that varies over time. More particularly, the channel estimation coefficients used in a channel estimator can be adapted based on an error signal representing the difference between a received signal at the timing recovery loop and an estimated signal output from a channel estimator. Further, to prevent undesirable interaction between the channel estimator and the overall timing recovery loop with respect to clock phase recovery, the adaptation of channel estimation can be controlled in terms of speed or time so as to reduce or eliminate the channel estimator's effect on clock phase correction.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: January 30, 2018
    Assignee: MACOM Connectivity Solutions, LLC
    Inventors: Yehuda Azenkot, Bart R. Zeydel
  • Patent number: 9882710
    Abstract: System and method of timing recovery for recovering a clock signal with reduced interaction between an adaptive channel estimator and the overall timing loop for correcting clock phase. The channel response estimation in the timing recovery loop is dynamically adapted to the current channel response that varies over time. The channel estimator includes compensation logic operable to detect and compensate a correction of clock phase ascribed to the channel estimator. The compensation logic can calculate the offset between a center of filter (COF) value and a COF nominal value, the offset indicative of the amount and direction of clock phase correction contributed by the channel estimator. Based on the offset, the compensation logic adjusts the estimates channel response by adjusting the tap weights of the channel estimator to correct the offset, thereby compensating the clock phase correction.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: January 30, 2018
    Assignee: MACOM Connectivity Solutions, LLC
    Inventors: Yehuda Azenkot, Bart R. Zeydel
  • Patent number: 9798672
    Abstract: Various aspects provide for managing data associated with a cache memory. For example, a system can include a cache memory and a memory controller. The cache memory stores data. The memory controller maintains a history profile for the data stored in the cache memory. In an implementation, the memory controller includes a filter component, a tagging component and a data management component. The filter component determines whether the data is previously stored in the cache memory based on a filter associated with a probabilistic data structure. The tagging component tags the data as recurrent data in response to a determination by the filter component that the data is previously stored in the cache memory. The data management component retains the data in the cache memory in response to the tagging of the data as the recurrent data.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: October 24, 2017
    Assignee: MACOM CONNECTIVITY SOLUTIONS, LLC
    Inventors: Kjeld Svendsen, John Gregory Favor
  • Patent number: 9787519
    Abstract: Cable systems and assemblies integrate a reduced number of twin axial cables to transmit and received in a full-duplex transmission signals at transmission speeds greater than or equal to one hundred Giga bytes per second. The reduced number of twin axial cables comprise four or less twin axial cables, in which each pair forms a single twin axial full-duplex cable for passive or active communication of the signals at multiple different transmission rates concurrently. A processor can be integrated with the twin axial cables and operate to encode the signals for fast transmission speeds at the different transmission rates.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: October 10, 2017
    Assignee: MACOM CONNECTIVITY SOLUTIONS, LLC
    Inventors: Dariush Dabiri, Tarun Gupta, Venkatesh Nagapudi
  • Patent number: 9781039
    Abstract: Systems and methods for multi-channel signal processing by a series of single processing core logic circuitries in time-slicing. A first logic circuitry is configured to process multiple data streams from multiple channels in a first cycle-based time-sliced schedule. A time slice in the first cycle-based time-sliced schedule comprises a predetermined number of clock cycles allocated to a corresponding data stream. A second logic circuitry is coupled to the first logic circuitry and configured to process the data streams in a first fragment-based time-sliced schedule. A time slice in the first fragment-based time-sliced schedule is determined based on a predetermined boundary associated with the data fragment and is allocated to process a data fragment of the data streams.
    Type: Grant
    Filed: December 6, 2013
    Date of Patent: October 3, 2017
    Assignee: MACOM Connectivity Solutions, LLC
    Inventor: Dimitri Mavroidis
  • Patent number: 9761521
    Abstract: Various embodiments provide for flexible and robust power grid connectivity in a server on a chip environment. The power grid has three parallel conductors, (e.g., wires) which represent two power polarities. The outside two wires can be of a first polarity (e.g. Vdd), while the middle wire is of a second polarity (e.g., Vss). The polarities of the wires can also be switched, as long as the two outside wires have the same polarity, while the inside wire has a different polarity. Power pins from modules adjacent to the set of three wires make connections to the nearest wire of the matching polarity. In this way, every power pin on the modules can be connected to the power grid without need for special alignment or custom power pins.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: September 12, 2017
    Assignee: MACOM CONNECTIVITY SOLUTIONS, LLC
    Inventors: Arun Jangity, Srini Gbalakrishnan, Tai Chong