Patents Assigned to MACOM Technology Solutions Holding, Inc.
  • TECHNIQUES FOR PROVIDING CURVED FACET SEMICONDUCTOR LASERS
    Publication number: 20190148911
    Abstract: Techniques for providing curved facet semiconductor lasers. are disclosed. In one particular embodiment, the techniques may be realized as a semiconductor laser, comprising a waveguide, wherein the waveguide includes a facet formed at an edge of the semiconductor laser, and the facet has a curvature.
    Type: Application
    Filed: November 15, 2018
    Publication date: May 16, 2019
    Applicant: MACOM Technology Solutions Holdings, Inc.
    Inventors: Youxi LIN, Wolfgang PARZ, Nathan BICKEL, Cristian STAGARESCU
  • De-emphasis with separate edge control
    Patent number: 10270217
    Abstract: A driver system with emphasis or de-emphasis control of optic signal generator comprising an input configured to receive an input signal that is to be transmitted as an optic signal. Also part of this system is a rising edge delay creating a first delay signal relative to the input signal and a falling edge delay creating a second delay signal relative to the input signal. A multiplexer receives the first delay signal and the second delay signal and selectively outputs either the first delay signal and the second delay signal to an amplifier. A first amplifier amplifies the input signal to create an amplified input and a second amplifier amplifies the multiplexer output signal to create a de-emphasis signal. A summing junction subtracts the de-emphasis signal from the amplified input to create a driver output signal. The rising and falling edge delays may each comprise two more delays.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: April 23, 2019
    Assignee: MACOM Technology Solutions Holdings, Inc.
    Inventor: Matteo Troiani
  • Driver with distributed architecture
    Patent number: 10263573
    Abstract: A distributed driver for an optic signal generator has a first amplifier cell with one or more amplifiers configured to receive and amplify an input signal to create a first amplified signal. A second amplifier cell has one or more amplifiers configured to receive and amplify the input signal to create a second amplified signal. A first conductive path and second conductive path connects to the first amplifier cell and the second amplifier cell such that the inductance associated with the first and second conductive path counteracts a capacitance associated with the first amplifier cell and the second amplifier cell. A variable capacitor may be part of the first amplifier cell and/or the second amplifier cell to selectively tune the capacitance of the distributed driver. A distributed bias circuit may be part of the first amplifier cell and/or the second amplifier cell to bias an optic signal transmitter.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: April 16, 2019
    Assignee: MACOM Technology Solutions Holdings, Inc.
    Inventors: Cristiano Bazzani, Matteo Troiani
  • OPERATIONAL TEMPERATURE DETERMINATION IN BIPOLAR TRANSISTORS BY RESISTANCE THERMOMETRY
    Publication number: 20190078941
    Abstract: Thermally-sensitive structure and methods for sensing the temperature in a region of a bipolar junction transistor (BJT) during device operation are described. The region may be at or near a region of highest temperature attained in the BJT. Metal resistance thermometry (MRT) can be implemented to assess a peak operating temperature of a BJT.
    Type: Application
    Filed: September 14, 2017
    Publication date: March 14, 2019
    Applicant: MACOM Technology Solutions Holdings, Inc.
    Inventors: Simon John Mahon, Allen W. Hanson
  • Electrical interface for package and die
    Patent number: 10212807
    Abstract: A circuit board and package assembly electrically connecting a die to a circuit board. The circuit board has signal paths terminating in a signal pad located on an insulating layer. The circuit board also includes a ground pad on the insulating layer that has a concave shaped side forming a recess, the with a signal pad at least partially within the recess. A package has package ground pads aligned with the circuit board ground pads and package signal pads aligned with circuit board signal pads. The package ground pads extend through the package to connect to package ground paths, which extend toward the die. The package signal pads extend through the package to connect to package signal paths and the package signal paths extend toward the die, maintaining a consistent distance from the package ground paths. Multiple-tier bond wires connect the package bond locations to the die bond pads.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: February 19, 2019
    Assignee: MACOM Technology Solutions Holdings, Inc.
    Inventor: Alfredo Moncayo
  • Alternating anti-parallel diode mixer structure
    Patent number: 10211780
    Abstract: An apparatus includes a first circuit and a second circuit. The first circuit may have a first diode and a second diode connected as anti-parallel diodes and physically adjacent to each other in a substrate. The second circuit may have a third diode and a fourth diode connected as anti-parallel diodes and physically adjacent to each other in the substrate. The first circuit and the second circuit may be configured to mix two input signals to generate an output signal. A polarity of every other physically neighboring diode may be reversed.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: February 19, 2019
    Assignee: MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC.
    Inventors: Emmanuelle R. O. Convert, Simon J. Mahon, James T. Harvey
  • Air cavity package
    Patent number: 10211113
    Abstract: A leadframe and air cavity packages formed using the leadframe are described. Using the leadframe, several air cavity packages can be quickly formed at one time. A method of manufacture using the leadframe can include forming the leadframe from a strip conductive material, where the leadframe includes conductive leads and downset facets. The method can also include forming slugs from conductive material, and arranging the slugs into respective positions relative to the downset facets of the leadframe. The method can also include fastening the slugs to the leadframe using the downset facets, and forming plastic packages around the leadframe and the slugs, where each of the plastic packages includes an air cavity in which at least a portion of a respective one of the slugs and at least a portion of a respective one of the conductive leads is exposed.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: February 19, 2019
    Assignee: MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC.
    Inventor: Quinn Don Martin
  • III-nitride semiconductor structures comprising low atomic mass species
    Patent number: 10211294
    Abstract: III-nitride materials are generally described herein, including material structures comprising III-nitride material regions and silicon-containing substrates. Certain embodiments are related to gallium nitride materials and material structures comprising gallium nitride material regions and silicon-containing substrates.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: February 19, 2019
    Assignee: MACOM Technology Solutions Holdings, Inc.
    Inventors: John Claassen Roberts, James W. Cook, Jr.
  • TECHNIQUES FOR HIGH SPEED OPTOELECTRONIC COUPLING BY REDIRECTION OF OPTICAL PATH
    Publication number: 20190052369
    Abstract: Techniques for high speed optoelectronic coupling by redirection of optical path are disclosed. In one particular embodiment, the techniques may be realized as an optoelectronic receiver comprising an optical signal demultiplexer that may be configured to transmit an optical signal along a first axis, and a photodiode that may be configured to convert the optical signal into an electrical signal, wherein the optical signal demultiplexer may include an inclined end surface that may be configured to reflect the optical signal towards a photoactive area of the photodiode at an obtuse angle of reflection with respect to the first axis.
    Type: Application
    Filed: February 2, 2018
    Publication date: February 14, 2019
    Applicant: MACOM Technology Solutions Holdings, Inc.
    Inventors: Xian-Li YEH, Cecile V. COHEN-JONATHAN, Boris GREK, C. Jacob SUN
  • Tuned semiconductor amplifier
    Patent number: 10204992
    Abstract: Methods and structures for improving the performance of integrated semiconductor transistors operating at high frequency and/or high power are described. Two capacitors may be connected to an input of a semiconductor transistor and tuned to suppress second-harmonic generation and to transform and match the input impedance of the device. A two-stage tuning procedure is described. The transistor may comprise gallium nitride and may be configured as a power transistor capable of handling up to 1000 W of power. A tuned transistor may operate at frequencies up to 6 GHz with a peak drain efficiency greater than 60%.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: February 12, 2019
    Assignee: MACOM Technology Solutions Holdings, Inc.
    Inventors: Walter H. Nagy, Lyndon Pattison
  • FET OPERATIONAL TEMPERATURE DETERMINATION BY FIELD PLATE RESISTANCE THERMOMETRY
    Publication number: 20190028066
    Abstract: Thermally-sensitive structures and methods for sensing the temperature in a region of a FET during device operation are described. The region may be at or near a region of highest temperature achieved in the FET. Metal resistance thermometry (MRT) can be implemented with gate or source structures to evaluate the temperature of the FET.
    Type: Application
    Filed: July 24, 2017
    Publication date: January 24, 2019
    Applicant: MACOM Technology Solutions Holdings, Inc.
    Inventors: Simon John Mahon, Allen W. Hanson
  • FET OPERATIONAL TEMPERATURE DETERMINATION BY GATE STRUCTURE RESISTANCE THERMOMETRY
    Publication number: 20190028065
    Abstract: Thermally-sensitive structures and methods for sensing the temperature in a region of a FET during device operation are described. The region may be at or near a region of highest temperature achieved in the FET. Metal resistance thermometry (MRT) can be implemented with gate or source structures to evaluate the temperature of the FET.
    Type: Application
    Filed: July 24, 2017
    Publication date: January 24, 2019
    Applicant: MACOM Technology Solutions Holdings, Inc.
    Inventors: Simon John Mahon, Allen W. Hanson
  • Semiconductor material having a compositionally-graded transition layer
    Patent number: 10177229
    Abstract: A semiconductor material includes a compositionally-graded transition layer, an intermediate later and a gallium nitride material layer. The compositionally-graded transition layer has a back surface and a top surface, and includes a gallium nitride alloy. The gallium concentration in the compositionally-graded transition layer increases from the back surface to the front surface. The intermediate layer is formed under the compositionally-graded transition layer. The gallium nitride material layer is formed over the compositionally-graded transition layer, and has a crack level of less than 0.005 ?m/?m2.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: January 8, 2019
    Assignee: MACOM Technology Solutions Holdings, Inc.
    Inventors: T. Warren Weeks, Jr., Edwin L. Piner, Thomas Gehrke, Kevin J. Linthicum
  • HIGH-POWER AMPLIFIER PACKAGE
    Publication number: 20190006297
    Abstract: Package assemblies for improving heat dissipation of high-power components in microwave circuits are described. A laminate that includes microwave circuitry may have cut-outs that allow high-power components to be mounted directly on a heat slug below the laminate. Electrical connections to circuitry on the laminate may be made with wire bonds. The packaging allows more flexible design and tuning of packaged microwave circuitry.
    Type: Application
    Filed: March 26, 2018
    Publication date: January 3, 2019
    Applicant: MACOM Technology Solutions Holdings, Inc.
    Inventor: Timothy Gittemeier
  • INTEGRATED SOLUTION FOR MULTI-VOLTAGE GENERATION WITH THERMAL PROTECTION
    Publication number: 20180358886
    Abstract: A multi-voltage converter is described that includes integrated temperature-protection circuity. The converter may be used to bias radio-frequency components such as PIN diodes and gallium-nitride devices, and may include integrated bias-sequencing circuitry. Programmable output voltages as high as 30 volts and as low as ?20 volts may be generated.
    Type: Application
    Filed: June 9, 2017
    Publication date: December 13, 2018
    Applicant: MACOM Technology Solution Holdings, Inc.
    Inventors: Andrew Patterson, Brendan Foley, Michelle Dowling
  • REDUCTION OF WAFER BOW DURING GROWTH OF EPITAXIAL FILMS
    Publication number: 20180358221
    Abstract: Structures and methods for reducing wafer bow during heteroepitaxial growth are described. Micro-trenches may be formed across a surface of a substrate and filled with polycrystalline material. Stress-relieving regions of material can be grown over the polycrystalline material in a layer of semiconductor material during heteroepitaxy.
    Type: Application
    Filed: June 7, 2017
    Publication date: December 13, 2018
    Applicant: MACOM Technology Solutions Holdings, Inc.
    Inventors: Douglas Carlson, Timothy E. Boles
  • Barrier for preventing eutectic break-through in through-substrate vias
    Patent number: 10147642
    Abstract: A method involving a barrier for preventing eutectic break-through in through-substrate vias is disclosed. The method generally includes steps (A) to (D). Step (A) may form one or more vias through a substrate. The substrate generally comprises a semiconductor. Step (B) may form a first metal layer. Step (C) may form a barrier layer. The barrier layer generally resides between the vias and the first metal layer. Step (D) may form a second metal layer. The second metal layer may be in electrical contact with the first metal layer through the vias and the barrier layer.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: December 4, 2018
    Assignee: MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC.
    Inventors: Allen W. Hanson, Rajesh Baskaran, Timothy E. Boles
  • TECHNIQUES FOR LASER ALIGNMENT IN PHOTONIC INTEGRATED CIRCUITS
    Publication number: 20180342851
    Abstract: Techniques for efficient alignment of a semiconductor laser in a Photonic Integrated Circuit (PIC) are disclosed. In some embodiments, a photonic integrated circuit (PIC) may include a semiconductor laser that includes a laser mating surface, and a substrate that includes a substrate mating surface. A shape of the laser mating surface and a shape of the substrate mating surface may be configured to align the semiconductor laser with the substrate in three dimensions.
    Type: Application
    Filed: July 16, 2018
    Publication date: November 29, 2018
    Applicant: MACOM Technology Solutions Holdings, Inc.
    Inventors: Roe HEMENWAY, Cristian STAGARESCU, Daniel MEEROVICH, Malcolm R. GREEN, Wolfgang PARZ, Jichi MA, Richard Robert GRZYBOWSKI, Nathan BICKEL
  • High power transistors
    Patent number: 10134658
    Abstract: High power transistors, such as high power gallium nitride (GaN) transistors, are described. These high power transistors have larger total gate widths than conventional high power transistors by arranging multiple linear arrays of gate, drain, and source contacts in parallel. Thereby, the total gate width and the power rating of the high power transistor may be increased without elongating the die of the high power transistor. Accordingly, the die of the high power transistor may be mounted in a smaller circuit package relative to conventional dies with the same power rating.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: November 20, 2018
    Assignee: MACOM Technology Solutions Holdings, Inc.
    Inventors: Aram Mkhitarian, Vincent Ngo
  • Integrated biasing for pin diode drivers
    Patent number: 10110218
    Abstract: Radio-frequency signals may be switched between signal lines or signal ports in RF circuits using PIN diodes and PIN-diode driving circuitry. To achieve switching, the PIN diodes are biased at voltages as high as 20 volts or more. Circuitry for biasing PIN diodes is described that uses a low-voltage power source and a single-bit control line.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: October 23, 2018
    Assignee: MACOM Technology Solutions Holdings, Inc.
    Inventors: Brendan Foley, Cristiano Bazzani, Michelle Dowling