Abstract: Semiconductor photonic device surfaces are covered with a dielectric or a metal protective layer. The protective layer covers the entire device, including regions near facets at active regions, to prevent bare or unprotected semiconductor regions, thereby to form a very high reliability etched facet photonic device.

Abstract: Semiconductor photonic device surfaces are covered with a dielectric or a metal protective layer. The protective layer covers the entire device, including regions near facets at active regions, to prevent bare or unprotected semiconductor regions, thereby to form a very high reliability etched facet photonic device.

Abstract: An optical signal module including a driver and an optical signal module. The driver includes a differential pair configured to receive and process an input signal to create a drive signal. A modulation current source provides a modulation current to the differential pair. One or more termination resistors connected to the differential pair for impedance matching. A first switch, responsive to a first control signal, maintains charge on a charge storage device. The optical signal module includes an optical signal generator arranged between a supply voltage node and a bias current node. The optical signal generator receives the drive signal and generates an optical signal representing the input signal. A second switch is between a supply voltage node the bias current node. The second switch, responsive to second control signal, selectively establishes a short between the supply voltage node the bias current node.

Abstract: A semiconductor laser may include a substrate, a multi quantum well (MQW) active layer, and an electron stopper layer. The MQW active layer may include a quantum well that is tensile strained and a barrier that is compressively strained. The barrier may be formed from an aluminum gallium indium arsenide phosphide alloy having a first AlxGayIn(1-x-y)AszP(1-z) composition. The electron stopper layer may include an aluminum gallium indium arsenide phosphide alloy having a second AlxGayIn(1-x-y)AszP(1-z) composition.

Abstract: A system and method for placing an inductor on a circuit board. This method includes providing a circuit board, a pedestal, and an inductor, the pedestal has a top surface and a bottom surface and the circuit board has one or more electrical conductors, the inductor having a first inductor terminal and a second inductor terminal. Adhesive is placed on the circuit board and the bottom surface of the pedestal is placed on the adhesive located on the circuit board to secure the pedestal to the circuit board. Next, adhesive is placed on the top surface of the pedestal and the inductor is placed on the adhesive located on the top surface of the pedestal to secure the inductor to the pedestal. The inductor is electrically connected to the circuit board.

Abstract: A semiconductor package and die assembly with a package having an exterior surface and an interior space, the interior space defined by a first side wall, and a second side wall that opposes the first side wall. Also part of the assembly is a package floor and a package ceiling. The package floor includes package floor conductors. The package ceiling opposes the package floor and includes package ceiling conductors in the package ceiling. One or more semiconductor dies are on the floor of the package floor. Electrical conductors electrically connect the one or more floor dies to the package floor conductors. One or more semiconductor dies are located on the package ceiling. Electrical conductors are configured to electrically connect the one or more ceiling dies to the package ceiling conductors. An air space is located between the package floor and the package ceiling.

Abstract: An apparatus includes a circuit and a shifter. The circuit may be configured to generate a control signal based on a reference voltage and a plurality of characteristics of an amplifier. The shifter may be configured to (i) receive an input signal carrying a pulse burst having a plurality of pulses, (ii) shift a plurality of phases of the pulses in the pulse burst in response to the control signal, and (iii) present the pulses as shifted in an output signal.

Abstract: Unidirectionality of lasers is enhanced by forming one or more etched gaps in the laser cavity. The gaps may be provided in any segment of a laser, such as any leg of a ring laser, or in one leg of a V-shaped laser. A Brewster angle facet at the distal end of a photonic device coupled to the laser reduces back-reflection into the laser cavity. A distributed Bragg reflector is used at the output of a laser to enhance the side-mode suppression ratio of the laser.

Abstract: An apparatus includes a radio frequency (RF) input port, an RF output port, a variable attenuation network, a first filter network, a second filter network, and a third filter network. The variable attenuation network may be coupled between the RF input port and the RF output port. Attenuation of the variable attenuation network is controlled by a first control signal and a second control signal. The first filter network may be connected between the RF input port and the RF output port. The second filter network may be connected between the variable attenuation network and a ground potential. The third filter network may be connected between the variable attenuation network and the ground potential. The first, the second, and the third filter networks modify performance of the variable attenuation network to produce a particular tilt of a radio frequency signal passing through the apparatus between the RF input port and the RF output port.

Abstract: A transistor circuit includes a main transistor having a gate terminal, a drain terminal and a source terminal, and a drain lag compensation circuit configured to sense a drain voltage on the drain terminal of the main transistor and to control a drain current through the main transistor based on the sensed drain voltage. The drain lag compensation circuit may include a reference transistor having a drain terminal coupled to a drain terminal of the main transistor, and a sensing circuit that is coupled to a source terminal of the reference transistor and provides a control voltage to a gate terminal of the main transistor. The reference transistor may be thermally coupled to the main transistor. The main transistor may be a GaN RF power transistor.

Abstract: An apparatus includes an input transformer, an amplifier and an output transformer. The input transformer may be on a substrate and configured to convert an input signal into a differential input signal. The input signal may be a radio-frequency signal. The amplifier may be on the substrate and configured to generate a differential output signal in response to the differential input signal. The amplifier may be a balanced and distributed amplifier. The output transformer may be on the substrate and configured to convert the differential output signal into an output signal. Each of the input transformer and the output transformer may be a three line coupled balun transformer with a variable bandpass bandwidth.

Abstract: System and method of timing recovery for recovering a clock signal with reduced interference with clock phase correction by an adaptive equalizer. The equalizer in the timing recovery loop is dynamically adapted to the current channel characteristics that vary over time. Upon a good Signal-to-Noise Ratio (SNR) being achieved, a selected set of the tap weights of the equalizer filter are frozen or set to smaller values, while others continue to adapt and the timing recovery loop continues the clock recovery process. Thereby, the adaptation of equalization can be adjusted to attenuate the equalization filter's effect on clock delay correction by limiting the adaptation time or speed relative to those of the entire timing recovery loop.

Abstract: A transimpedance amplifier that includes an input configured to receive a current input from an upstream device and output configured to present an output voltage. The current input may be from a photodetector or any other device that is part of an optical signal receiving unit front end. In one configuration, there are three amplifier stages in the transimpedance amplifier connected in series. A feedback path with feedback resistor connects between the input and output of the transimpedance amplifier. A bandwidth extender circuit connects between a stage output and a stage input of the transimpedance amplifier. In a three stage embodiment, the bandwidth extender circuit extends between an input of the second stage and the output of the second stage. The bandwidth extender includes at least one active device configured to provide positive feedback to increase gain. The bandwidth extender circuit is able to be automatically or selectively deactivated to filter unwanted frequency components.

Abstract: A laser chip having a substrate, an epitaxial structure on the substrate, the epitaxial structure including an active region and the active region generating light, a waveguide formed in the epitaxial structure extending in a first direction, the waveguide having a front etched facet and a back etched facet that define an edge-emitting laser, and a first recessed region formed in the epitaxial structure, the first recessed region being arranged at a distance from the waveguide and having an opening adjacent to the back etched facet, the first recessed region facilitating testing of an adjacent laser chip prior to singulation of the laser chip.

Abstract: A voltage controlled oscillator includes a variable capacitance circuit having a plurality of variable capacitance elements, each having a capacitance that is a function of a tuning voltage, two or more oscillator core circuits, each operable over a specified frequency band, and inductive elements connected between the variable capacitance circuit and the oscillator core circuits.

Abstract: Techniques for efficient alignment of a semiconductor laser in a Photonic Integrated Circuit (PIC) are disclosed. In some embodiments, a photonic integrated circuit (PIC) may include a semiconductor laser that includes a laser mating surface, and a substrate that includes a substrate mating surface. A shape of the laser mating surface and a shape of the substrate mating surface may be configured to align the semiconductor laser with the substrate in three dimensions.

Abstract: An apparatus includes a first directional coupler, a second directional coupler, a first detector, and a second detector. A through port of the first directional coupler is coupled to a through port of the second directional coupler. An isolated port of the first directional coupler is coupled to an isolated port of the second directional coupler. A coupled port of the first directional coupler is coupled to the first detector. A coupled port of the second directional coupler is coupled to the second detector. A detected power signal is generated by combining an output of the first detector and an output of the second detector.

Abstract: Multi-way amplifiers having impedance inverters connected to outputs of one or more peaking amplifiers are described. The output of the main amplifier may connect directly to a combining node and output impedance matching network. The multi-way amplifier configuration can improve efficiency at power back-off and improve RF bandwidth.

Abstract: An apparatus includes a first gain stage, a combiner and a second gain stage. The first gain stage may be configured to amplify a receive signal acquired from a circuit to generate an intermediate signal. The combiner may be configured to combine the intermediate signal with a cancellation signal to generate a combined signal. The cancellation signal is generally derived from a transmit signal a portion of which appears in the receive signal through the circuit. The second gain stage may be configured to amplify the combined signal to generate an output signal.

Abstract: III-nitride materials are generally described herein, including material structures comprising III-nitride material regions and silicon-containing substrates. Certain embodiments are related to gallium nitride materials and material structures comprising gallium nitride material regions and silicon-containing substrates.