Abstract: A buffer circuit includes an input stage configured to provide a differential current to a load stage or receive the differential current from the load stage based on a difference between an input voltage and an output voltage, wherein the load stage is configured to apply gate voltages to first and second output transistors of an output stage, and wherein the output stage is configured to regulate the output voltage; a slew rate compensation circuit configured to provide a slew rate compensation current to the load stage or receive the slew rate compensation current from the load stage; an offset control signal output stage configured to output an offset control signal by being applied with first and second N-bit control signals; and an offset blocking circuit comprising a switch configured to turn off a current source of the slew rate compensation circuit by the offset control signal.

Abstract: A display driving device for driving a display panel includes a timing controller configured to output a bias control signal and video data based on a display brightness value (DBV) received from an external source; and a source driver configured to output a data line voltage to a plurality of channels based on the bias control signal and the video data.

Abstract: A display driving IC includes first channel block to Nth channel block each including M source amplifiers, N and M being an integer, source driving pads each connected to the M source amplifiers, a multiplexer configured to alternate data outputs of the source amplifiers or selectively provide a test path so that a probe test is performed on a plurality of source amplifiers for each of the first to Nth channel blocks through a test pad selected from the source driving pads, and a control unit configured to control driving of the source amplifiers and multiplexer.

Abstract: A switch control circuit and switch control method are provided. The switch control circuit and switch control method compensate an error of a load current that occurs because of the changing of a slope of an inductor current based on the increase and decrease of an input voltage. The switch control circuit includes a current compensation device that adjusts a gate on time based on a RC resistor and a control signal that senses a gate terminal of a control switch. The current compensation device compensates an error that occurs due to a signal delay to a gate terminal by increasing or decreasing a reference voltage or a sensing voltage, according to an increase or a decrease of an input voltage.

Abstract: A mask layout for forming a semiconductor device includes an active mask pattern, a gate electrode mask pattern, a silicide blocking mask pattern, and a contact mask pattern. The active mask pattern forms source and drain regions in a substrate. The gate electrode mask pattern, disposed to overlap the active mask pattern, forms a gate electrode between the source region and the drain region. The silicide blocking mask pattern is disposed to overlap the gate electrode mask pattern and the active mask pattern in the gate electrode, the source region, and the drain regions to form a silicide blocking region. The contact mask pattern, disposed spaced apart from the silicide blocking mask pattern, forms a contact plug on the substrate. The silicide blocking mask pattern covers the gate electrode mask pattern and extends to the active mask pattern.

Abstract: A display device includes a timing controller configured to generate first option data, second option data, a first option enable signal, and a second option enable signal based on image data; a gamma voltage generator configured to output a plurality of gamma voltages; and a source driver including a plurality of switches and configured to receive the plurality of gamma voltages through a plurality of gamma lines. The source driver is configured to adjust turn-on timing of the plurality of switches based on the first and second option data and the first and second option enable signals to reduce a recovery time of the gamma lines.

Abstract: A display drive device configured to drive a display panel includes a timing controller configured to compare current data to previous data based on a channel unit in horizontal time, calculate data difference values, and output a bias control signal determined based on a maximum value among the calculated data difference values; and a source driver configured to generate a bias current based on the bias control signal and based on the channel unit. The source driver includes an output circuit configured to output a data signal to a plurality of channels based on the bias current generated based on the channel unit.

Abstract: A semiconductor device includes an active area and a junction termination area, each including a drain electrode, a first epitaxial layer of a first conductivity type disposed on the drain electrode, and a second epitaxial layer of the first conductivity type disposed on the first epitaxial layer. The junction termination area further includes a first junction termination area etched on a portion of the second epitaxial layer, and a second junction termination area that is not etched. A field oxide layer is disposed on a portion of the first junction termination area. A doped region of a second conductivity type is disposed to extend from beneath the field oxide layer to the second junction termination area.

Abstract: A regulator circuit includes a first regulator configured to supply a first current to a VDD pad connected to a power line based on a first output voltage, and a second regulator configured to supply a second current to the VDD pad based on a second output voltage. The second output voltage has dropped by a predetermined delta voltage from the first output voltage.

Abstract: An electronic device includes a first electronic device and a second electronic device configured to transmit and receive signals based on a C-PHY protocol. The second electronic device includes a calibrator configured to receive recovered data via a data path used to receive real data and provide a calibration value; and a clock recoverer configured to recover a clock signal (CLK) using the calibration value.

Abstract: The display device includes a display panel including a plurality of pixels; a driver IC configured to convert digital data corresponding to an input image to an analog voltage using a gamma voltage, and to supply the analog voltage to the plurality of pixels; and a power supply configured to supply a pixel driving voltage to the display panel and the driver IC. The driver IC includes a weight selector configured to select a weight for adjusting the gamma voltage based on a change amount of the pixel driving voltage supplied from the power supply; and a gamma reference voltage generating unit configured to generate a gamma reference voltage based on the selected weight.

Abstract: A skew correction circuit includes a skew value detector configured to delay input data and detect a skew correction value for performing skew correction between a data signal and a clock signal, the skew value detector including a first comparator configured to compare the input data with a capture clock signal and detect a Pass or Fail result; and a controller configured to utilize the skew correction value detected.

Abstract: A super-junction semiconductor device includes a substrate; an active cell disposed on the substrate; an edge termination region configured to surround the active cell; a peripheral region configured to surround the active cell and disposed between the active region and the edge termination region; a first conductivity-type pillar and a second conductivity-type pillar alternately disposed in the active cell, the peripheral region, and the edge termination region; a horizontal-shaped second conductivity-type pillar region disposed on the second conductivity-type pillar in the peripheral region and the edge termination region; and a second conductivity-type charge-sharing region disposed on the horizontal-shaped second conductivity-type pillar region.

Abstract: A power semiconductor with a Schottky contact structure includes gate regions spaced apart by a predetermined interval in a first direction; a highly doped source region of a first conductivity-type positioned between the gate regions; a source contact region disposed on the highly doped source region of the first conductivity-type; a plurality of buried pillar regions of a second conductivity-type spaced at a preset interval in a second direction intersecting the first direction; and Schottky contact regions formed at a point where the plurality of buried pillar regions of the second conductivity-type intersect with the gate regions.

Abstract: A method for manufacturing a trench MOSFET device includes forming a trench in an epitaxial layer, forming a shield oxide and a shield poly in the trench, etching the shield poly to leave only a portion of the shield poly, forming an inter poly oxide (IPO) on the shield oxide and shield poly, etching the IPO and the shield oxide, leaving a portion of the IPO on an upper surface of the shield poly and the shield oxide, forming a first gate sacrificial oxide layer by performing a deposition process, forming a second gate sacrificial oxide layer on the first gate sacrificial oxide layer by performing a thermal oxidation process, and performing an etching process to leave a gate sacrificial oxide layer at a boundary between a sidewall of an interior of the trench and the upper surface of the shield oxide.

Abstract: A super junction semiconductor device includes a substrate; a plurality of epitaxial layers disposed on the substrate; an active region disposed on one region of the substrate and the epitaxial layer; a peripheral region and an edge termination region surrounding the active region; and a plurality of first conductive type pillar regions and a plurality of second conductive type pillar regions disposed in the plurality of epitaxial layers, respectively. Each of the plurality of first conductive type pillar regions and the plurality of second conductive type pillar regions in the active region is divided into a lower pillar region, an intermediate pillar region, and an upper pillar region, sequentially. A dopant concentration gradually increases from the lower pillar region to the intermediate pillar region, and another dopant concentration gradually decreases from the intermediate pillar region to the upper pillar region.

Abstract: A wafer level chip scale package includes a semiconductor substrate having a first thickness, an input-output pad formed on the semiconductor substrate, a front metal layer having a second thickness formed on the input-output pad, a back metal layer having a third thickness formed on a bottom of the semiconductor substrate, and a metal bump formed on the semiconductor substrate.

Abstract: A semiconductor die forming method includes preparing a wafer, forming a low-k dielectric layer on the wafer, forming a metal pad on the low-k dielectric layer, forming a passivation layer on the metal pad, patterning the passivation layer, laser grooving the low-k dielectric layer using an ultrashort pulse laser, and cutting the wafer by mechanical sawing to form one or more semiconductor dies.

Abstract: A buffer circuit configured to generate an output voltage according to an input voltage includes: an input stage configured to provide first and second differential currents to a load stage or receive third and fourth differential currents from the load stage based on a difference between the input voltage and the output voltage; a load stage configured to apply gate voltages to first and second output transistors of an output stage based on the first through fourth differential currents; the output stage configured to regulate the output voltage based on the gate voltages applied to the first and the second output transistors; and a slew rate compensator configured to regulate the gate voltages of the first and second output transistors by providing a source current to the load stage or receiving a sink current from the load stage.

Abstract: A display device includes: a display panel including a plurality of pixels, a driver integrated circuit (IC) configured to convert digital data corresponding to an input image to an analog data voltage using a gamma voltage, and to supply the analog data voltage to the plurality of pixels, and a power supply configured to supply a pixel driving voltage to the display panel and the driver IC, and the driver IC includes: a weight selector configured to select a weight for adjusting the gamma voltage based on an amount of change in the pixel driving voltage supplied from the power supply, and a gamma reference voltage generating circuit configured to generate a gamma reference voltage based on the selected weight.