Abstract: A current generating circuit includes a current generator configured to supply a reference current, switches connected to the current generator, wherein one switch of the switches is selected and configured to operate, according to a switch selection signal, and one or more resistors, respectively connected to the switches, wherein a rate of current change according to a temperature change of the current generator is adjusted based on a temperature coefficient of resistance (TCR) of resistors connected to the one switch, according to adjustment of the one switch.

Abstract: A semiconductor die forming method includes preparing a wafer, forming a low-k dielectric layer on the wafer, forming a metal pad on the low-k dielectric layer, forming a passivation layer on the metal pad, patterning the passivation layer, laser grooving the low-k dielectric layer using an ultrashort pulse laser, and cutting the wafer by mechanical sawing to form one or more semiconductor dies.

Abstract: A device includes a clock delay circuit configured to receive a reference clock signal and generate N delay clock signals, where N is a natural number greater than or equal to 2, by using the reference clock signal, and an output circuit configured to receive the N delay clock signals and output at least a portion of the delay clock signals from among the N delay clock signals as an output signal, wherein a phase delay of a delay clock signal that is output later in time from among the at least the portion of the delay clock signals is greater than or equal to a phase delay of a delay clock signal that is output earlier in time, and wherein a cycle of the output clock signal is longer than or equal to a cycle of the reference clock signal.

Abstract: A panel control circuit for controlling a display panel comprising a first data line and a second data line includes a timing controller configured to generate input data comprising a first input data and a second input data, a first driving circuit configured to output a first video signal corresponding to the first input data into the first data line, and a second driving circuit configured to output a second video signal corresponding to the second input data into the second data line, wherein the timing controller is configured to turn off the second driving circuit based on a first deviation, a second deviation, or a third deviation.

Abstract: A multi-vision display device includes a timing controller, a plurality of display panels, and a plurality of display driver integrated circuits (ICs). The timing controller is configured to receive source data and timing signals from a host, and generate a data packet comprising image data and control data. The plurality of display driver ICs each is connected to any one of the plurality of display panels. The control data includes a panel identifier indicating a number of display panels of the plurality of display panels connected to the display driver IC prior to a corresponding display panel connected to the display driver IC. Adjacent ones of the plurality of display driver ICs are connected to each other, modulate the panel identifier provided from one among the timing controller and a front end display driver IC, and provide the modulated panel identifier to a rear end display driver IC.

Abstract: A panel control circuit configured to control a display panel includes a plurality of pixels. The panel control circuit includes a controller configured to output an image data and a source driver, including an output circuit and an output control circuit, configured to generate data signals based on the image data. The controller is configured to output an output change signal for changing an output of the source driver. The output circuit is configured to output the data signals to the display panel, and the output control circuit is configured to output an adjusting current to the output circuit in a signal transition section of the output change signal.

Abstract: A driving device of a flat panel display configured to receive an image signal and a clock signal includes a driving circuit configured to convert the image signal into pixel data and output the pixel data, a timing controller configured to generate and output a vertical synchronization signal, a horizontal synchronization signal, a source change enable signal, and a display enable signal using the image signal and the clock signal, an output buffer including an input terminal configured to receive the pixel data and an output terminal connected to the flat panel display, and a buffer controller connected to the timing controller and the output buffer and configured to control a bias current, applied to the output buffer, to be decreased by a value during a period.

Abstract: A semiconductor device manufacturing method includes forming a first trench insulating film of a first depth in a substrate, forming at least one second trench insulating film that is spaced apart from the first trench insulating film and has a second depth that is greater than the first depth, forming a body region of a first conductivity type and a drift region of a second conductivity type in the substrate, forming a gate electrode overlapping the first trench insulating film, forming a source region in the body region and a drain region in the drift region, forming a silicide film on the drain region, and forming a non-silicide film between the first trench insulating film and the drain region, wherein the first trench insulating film overlaps the drift region and the gate electrode.

Abstract: A semiconductor device includes a source region, a drain region, and a gate insulating film formed on a substrate, a gate electrode formed on the gate insulating film, a first insulating film pattern formed to extend from the source region to a part of a top surface of the gate electrode, and a spacer formed on a side surface of the gate electrode in a direction of the drain region.

Abstract: A gamma correction circuit includes an input circuit configured to sequentially receive gamma control signals used for selecting gamma tap points from a control circuit through a single transmission line, and to output the received gamma control signals, and a voltage generator configured to select the gamma tap points based on the gamma control signals, and to generate gamma voltages according to the gamma tap points.

Abstract: A semiconductor device includes a substrate, a first P-type well region and a second P-type well region disposed in the substrate, wherein the first P-type well region and the second P-type well region are spaced apart from each other, an N-type source region disposed in the substrate, wherein the N-type source region is disposed spaced apart from the second P-type well region, an N-type drain region disposed in the second P-type well region, an N-type LDD region disposed near the N-type drain region, and a gate insulating layer and a gate electrode on the substrate, wherein the gate electrode partially overlaps the second P-type well region.

Abstract: A display driver for driving a display panel includes a first driving circuit configured to output a first image signal to a first output pad, and a second driving circuit configured to output a second image signal to a second output pad; and the first driving circuit is further configured to output a reference image signal to the second driving circuit in response to a power down signal, and the second driving circuit is further configured to output the reference image signal output from the first driving circuit to the second output pad in response to the power down signal.

Abstract: A semiconductor chip packaging method includes forming a bump on a wafer, forming a coating film covering the bump, laser grooving the wafer, plasma etching the wafer on which the laser grooving is performed, exposing the bump by removing the coating film covering the bump, fabricating a semiconductor die by performing mechanical sawing of the wafer, and packaging the semiconductor die.

Abstract: A method for manufacturing a power semiconductor device includes forming a drift region in a substrate, forming a trench in the drift region, forming a gate insulating layer in the trench, depositing a conductive material on the substrate, forming a gate electrode in the trench, forming a body region in the substrate, forming a highly doped source region in the body region, forming an insulating layer that covers the gate electrode, etching the insulating layer to open the body region, implanting a dopant into a portion of the body region to form a highly doped body contact region, so that the highly doped source region and the highly doped body contact region are alternately formed in the body region; and forming a source electrode on the highly doped body contact region and the highly doped source region.

Abstract: A reception apparatus communicating with a transmission apparatus with a clock lane and a data lane. The reception apparatus comprises a clock lane control circuit configured to determine the operation mode of the clock lane based on a clock signal transmitted through the clock lane, and performing an operation based on the determined operation mode of the clock lane, and a data lane control circuit configured to determine the operation mode of the data lane based on a data signal transmitted from the transmission apparatus, and performing an operation based on the determined operation mode of the data lane, and the clock lane control circuit is configured to set the operation mode of the clock lane to a high-speed mode, when the operation mode of the data lane is switched from a low-power mode to the high-speed mode.

Abstract: The present disclosure relates to a semiconductor chip having a level shifter with electro-static discharge (ESD) protection circuit and device applied to multiple power supply lines with high and low power input to protect the level shifter from the static ESD stress. More particularly, the present disclosure relates to a feature to protect a semiconductor device in a level shifter from the ESD stress by using ESD stress blocking region adjacent to a gate electrode of the semiconductor device. The ESD stress blocking region increases a gate resistance of the semiconductor device, which results in reducing the ESD stress applied to the semiconductor device.

Abstract: A mask layout for forming a semiconductor device includes an active mask pattern, a gate electrode mask pattern, a silicide blocking mask pattern, and a contact mask pattern. The active mask pattern forms source and drain regions in a substrate. The gate electrode mask pattern, disposed to overlap the active mask pattern, forms a gate electrode between the source region and the drain region. The silicide blocking mask pattern is disposed to overlap the gate electrode mask pattern and the active mask pattern in the gate electrode, the source region, and the drain regions to form a silicide blocking region. The contact mask pattern, disposed spaced apart from the silicide blocking mask pattern, forms a contact plug on the substrate. The silicide blocking mask pattern covers the gate electrode mask pattern and extends to the active mask pattern.

Abstract: A method to manufacture a semiconductor package includes: preparing a metal substrate; attaching semiconductor dies to the metal substrate at an interval; attaching a bonding film to the semiconductor dies; applying a mold material on the semiconductor dies and the metal substrate, and curing the mold material to form a mold member; grinding the mold member and the metal substrate to a thickness; removing the bonding film; attaching a redistribution layer to the semiconductor dies; and cutting between the semiconductor dies.

Abstract: A semiconductor device includes a substrate, a counter-doping region, and a Schottky barrier diode (SBD) in which a breakdown voltage is improved by using counter doping, and a manufacturing method thereof. A breakdown voltage may be improved by lowering a concentration of impurity on the region and enhancing the characteristics of the semiconductor device including the SBD.

Abstract: A method for manufacturing a power semiconductor device includes forming a drift region in a substrate, forming a trench in the drift region, forming a gate insulating layer in the trench, depositing a conductive material on the substrate, forming a gate electrode in the trench, forming a body region in the substrate, forming a highly doped source region in the body region, forming an insulating layer that covers the gate electrode, etching the insulating layer to open the body region, implanting a dopant into a portion of the body region to form a highly doped body contact region, so that the highly doped source region and the highly doped body contact region are alternately formed in the body region; and forming a source electrode on the highly doped body contact region and the highly doped source region.