Abstract: A semiconductor device includes: a semiconductor substrate; an epitaxial layer disposed on the substrate; a plurality of trenches formed in the epitaxial layer; a shield insulating layer formed inside the plurality of trenches; a shield electrode surrounded by the shield insulating layer and disposed inside the plurality of trenches; an inter-electrode insulating layer formed on top of the shield insulating layer and the shield electrode; a gate insulating layer disposed on the inter-electrode insulating layer; a gate electrode disposed on the gate insulating layer; a body region formed on an upper portion of the epitaxial layer located between the plurality of trenches; a source region formed on the body region; an inter-layer insulating layer formed on the gate electrode and the source region; and a body contact region in contact with the source region and the body region.

Abstract: A fast recovery diode includes a substrate; an epitaxial layer formed on the substrate; a P-type low-concentration doping region formed in an upper portion of the epitaxial layer and a P-type high-concentration doping region formed on the P-type low-concentration doping region; a P-type guard ring formed in the upper portion of the epitaxial layer to surround the P-type low-concentration doping region and P-type high-concentration doping region; a field oxide layer formed on the P-type guard ring and the P-type high-concentration doping region; an anode electrode formed to overlap the P-type high-concentration doping region and a portion of the field oxide layer; and a cathode electrode formed below the substrate.

Abstract: The present disclosure relates to a semiconductor chip having a level shifter with electro-static discharge (ESD) protection circuit and device applied to multiple power supply lines with high and low power input to protect the level shifter from the static ESD stress. More particularly, the present disclosure relates to a feature to protect a semiconductor device in a level shifter from the ESD stress by using ESD stress blocking region adjacent to a gate electrode of the semiconductor device. The ESD stress blocking region increases a gate resistance of the semiconductor device, which results in reducing the ESD stress applied to the semiconductor device.

Abstract: A multichip package and a method for manufacturing the same are provided. A multichip package includes: a plurality of semiconductor chips each mounted on corresponding lead frame pads; lead frames connected to the semiconductor chips by a bonding wire; and fixed frames integrally formed with at least one of the lead frame pads and configured to support the lead frame pads on a package-forming substrate.

Abstract: A super junction semiconductor device includes a substrate, an active cell disposed on the substrate, an edge termination region surrounding the active cell, a peripheral region formed between the active cell and the edge termination region, a plurality of first conductivity type pillars and second conductivity type pillars alternately provided at an edge of the active cell and the peripheral region and the edge termination region, and a charge sharing region connecting the second conductivity type pillars in the peripheral region with the second conductivity type pillars in the edge termination region above the peripheral region and the edge termination region.

Abstract: A memory repair device for detecting a fault cell in a memory and replacing it with a redundancy cell using a serial interface method is provided. The memory repair device include a repair information control block and at least one memory block including at least one memory. The repair information control block is configured to perform a built-in self-test (BIST) for each memory block, and when a fault cell is detected according to the BIST, receive and store repair information about the fault cell information. The memory block replaced the fault cell with a redundancy cell according to repair information loaded by the repair information control block at the time of operation of the memory. Data is transmitted and received between the repair information control block and the memory block using a serial interface.

Abstract: The present disclosure relates to a deadlock recovery unit for applying a one-shot pulse signal to restart a Voltage Controlled Oscillator (VCO) when the output clock signal of the VCO remains in a high state or a low state. The deadlock recovery unit includes a VCO clock monitoring unit for monitoring a clock signal of a voltage control oscillator; a pulse signal generating unit for outputting a one-shot pulse signal to reset the VCO when a clock signal is not counted; and a control signal generating unit for generating a VCO counter enable signal applied to the VCO clock monitoring unit and a detector clock signal applied to the pulse signal generating unit by using an externally supplied reference clock signal.

Abstract: A negative level shifter that connects a source terminal and a body region of an element included in a shielding circuit so that the element operates within a medium voltage operating region. The negative level shifter of the present disclosure connects the source terminal and the body region of the shielding circuit so that the voltage between the drain terminal of the shielding circuit and the body region required for negative level shifting is operated in the medium voltage operating region. In addition, the negative level shifter may be able to use a medium voltage transistor rather than a high voltage transistor element provided in the input circuit so that the design area will be reduced compared to the conventional art. Also, the present disclosure suggests a display device with a negative level shifter.

Abstract: A semiconductor device includes a semiconductor substrate; an oxide film formed on the semiconductor substrate; a gate poly formed on a portion of the oxide film; a spacer formed to surround the gate poly; a dielectric film formed on the spacer; a first barrier metal formed on side surfaces of the oxide film, the gate poly, the spacer, and the dielectric film which are stacked, a surface of the semiconductor substrate, and a top surface of the dielectric film; a second barrier metal formed on the first barrier metal; a metal plug formed in a cavity formed by the second barrier metal; a metal layer formed on the second barrier metal and the metal plug; and a passivation layer formed on the metal layer. A thickness of the first barrier metal formed on the surface of the dielectric film is in a range of from 15 nm to 25 nm.

Abstract: A wafer annealing apparatus includes a gas supply unit located on one side of the wafer annealing apparatus and configured to supply high-temperature gases to transfer heat to wafers loaded inside the wafer annealing apparatus, a rotation driving unit comprising a rotation controller and configured to rotate a wafer support unit loaded with wafers, and a gas release unit located on the other side of the wafer annealing apparatus and configured to release the high-temperature gases fed to the wafer annealing apparatus. The rotation controller includes at least one processor configured to transmit a control signal to the rotation driving unit and control a rotation cycle and a rotation angle of the rotation driving unit.

Abstract: A regulator circuit includes a first regulator configured to supply a first current to a VDD pad connected to a power line based on a first output voltage, and a second regulator configured to supply a second current to the VDD pad based on a second output voltage. The second output voltage has dropped by a predetermined delta voltage from the first output voltage.

Abstract: A display driving IC includes first channel block to Nth channel block each including M source amplifiers, N and M being an integer, source driving pads each connected to the M source amplifiers, a multiplexer configured to alternate data outputs of the source amplifiers or selectively provide a test path so that a probe test is performed on a plurality of source amplifiers for each of the first to Nth channel blocks through a test pad selected from the source driving pads, and a control unit configured to control driving of the source amplifiers and multiplexer.

Abstract: A semiconductor device includes a source region, a drain region, and a gate insulating film formed on a substrate, a gate electrode formed on the gate insulating film, a first insulating film pattern formed to extend from the source region to a part of a top surface of the gate electrode, and a spacer formed on a side surface of the gate electrode in a direction of the drain region.

Abstract: The present disclosure relates to a temperature sensor provided in a display driver circuit and an operating method thereof. Disclosed is a temperature sensor provided in a display driver circuit including: a reference voltage generating unit configured to output a set reference voltage; a proportional voltage generating unit configured to output a proportional voltage proportional to a temperature of the circuit; a comparison unit configured to output a flag voltage by comparing magnitudes of the reference voltage and the proportional voltage; and a sensor control unit configured to control the reference voltage generating unit and the proportional voltage generating unit.

Abstract: A power source switching circuit for a memory device includes: a first power source voltage terminal for supplying a first power source voltage, a second power source voltage terminal for supplying a second power source voltage, a first metal-oxide-semiconductor field-effect transistor (MOSFET) and a second MOSFET connected in series with the first power source voltage terminal, a first level shifter connected to the first MOSFET and supplied with the first power source voltage, a second level shifter connected to the second MOSFET and supplied with the second power source voltage, a third MOSFET connected to the second MOSFET, and a third level shifter connected to the third MOSFET and supplied with a third power source voltage, and a memory cell of a non-volatile memory is programmed using the first power source voltage or the second power source voltage.

Abstract: A source driver for a display panel includes an output buffer configured to output a signal to a data line of the display panel; an output controller configured to control an output of the output buffer; a load resistance measuring unit configured to measure a load resistance of at least one data line of the display panel; and a comparison unit configured to compare the load resistance measured in the load resistance measuring unit with an initial load resistance, wherein the output controller is further configured to control a signal to be output by the output buffer based on the comparison result.

Abstract: A memory repair device for detecting a fault cell in a memory and replacing it with a redundancy cell using a serial interface method is provided. The memory repair device include a repair information control block and at least one memory block including at least one memory. The repair information control block is configured to perform a built-in self-test (BIST) for each memory block, and when a fault cell is detected according to the BIST, receive and store repair information about the fault cell information. The memory block replaced the fault cell with a redundancy cell according to repair information loaded by the repair information control block at the time of operation of the memory. Data is transmitted and received between the repair information control block and the memory block using a serial interface.

Abstract: A method for forming a semiconductor die, includes forming an interlayer dielectric layer on a substrate having a semiconductor die region, a seal-ring region, and a scribe line region, forming a metal pad and a test pad on the interlayer dielectric layer, forming a passivation dielectric layer on the interlayer dielectric layer, the metal pad, and the test pad, first etching the passivation dielectric layer and the interlayer dielectric layer existing between the seal-ring region and the scribe line region to a predetermined depth using a plasma etching process, second etching the passivation dielectric layer to expose the metal pad and the test pad, forming a bump on the metal pad, and dicing the substrate while removing the scribe line region by mechanical sawing.

Abstract: A switch control circuit and a switch control method are provided. In this circuit, compositions that sense a drain voltage of a switch device are added in a QR Buck Converter switch control circuit. A first resistor, a second switch, a second resistor are electrically connected to a drain terminal of a switch device to sense the 0 A state of an inductor current. On the basis of a detection result, the switch control circuit turns on the switch device when an inductor current is 0 A, and a drain sensing voltage (ZCD) is less than a predetermined reference voltage (REF).

Abstract: A slew rate adjusting circuit includes an adjustment transistor configured to provide an adjustment current into an output port of an arithmetic amplifier, a first transistor connected between a power line of the arithmetic amplifier and the adjustment transistor, and a second transistor connected between the first transistor and an output node of the output port, wherein the adjustment transistor is turned on by the second transistor in response to a difference between an input voltage and an output voltage being equal to or greater than a reference voltage, and the adjustment current is provided to the output port in response to the adjustment transistor being turned on.