Abstract: A slew rate adjusting circuit includes an adjustment transistor configured to provide an adjustment current into an output port of an arithmetic amplifier, a first transistor connected between a power line of the arithmetic amplifier and the adjustment transistor, and a second transistor connected between the first transistor and an output node of the output port, wherein the adjustment transistor is turned on by the second transistor in response to a difference between an input voltage and an output voltage being equal to or greater than a reference voltage, and the adjustment current is provided to the output port in response to the adjustment transistor being turned on.

Abstract: A switch control circuit and switch control method are provided. The switch control circuit and switch control method compensate an error of a load current that occurs because of the changing of a slope of an inductor current based on the increase and decrease of an input voltage. The switch control circuit includes a current compensation device that adjusts a gate on time based on a RC resistor and a control signal that senses a gate terminal of a control switch. The current compensation device compensates an error that occurs due to a signal delay to a gate terminal by increasing or decreasing a reference voltage or a sensing voltage, according to an increase or a decrease of an input voltage.

Abstract: A fault handling apparatus and a fault handling method which perform a built-in self-test (BIST) and a repair on a static random-access memory (SRAM) cell, and the fault handling apparatus and the fault handling method store the fault and repair history information of a previous SRAM test, provide the information to a current test, and reflect both BIST results and the information on the previous test, thereby performing multiple repairs until there is no available spare SRAM.

Abstract: A switch control circuit and a switch control method are provided. The switch control circuit includes a load, an inductor, a control switch, and a sensing resistance connected in series to an input power; an integrator that integrates a sensing voltage and a load current setting voltage to generate an integrated signal; a comparator that compares the integrated signal and a bias voltage; a switch driver that controls the control switch based on an output of the comparator and an output of an off time controller; and a gate sensor that outputs, to the integrator, a gate sensing signal that senses a time when an input of a gate terminal of the control switch becomes a low level. An integration operation is started from a position in which the integrated signal is located lower than the bias voltage, when an input of the gate terminal becomes a high level.

Abstract: A transmission driver includes a pulse generator and a current mode logic driver. The pulse generator is configured to generate and output a first pulse signal by synchronizing at a falling edge time point of a first input signal, and generate and output a second pulse signal by synchronizing at a falling edge time point of a second input signal. The current mode logic driver is configured to output a pre-emphasis signal to which pre-emphasis technique has been applied by changing a first load resistance value and a second load resistance value based on the first pulse signal and the second pulse signal, respectively.

Abstract: A semiconductor device includes a source region, a drain region, and a gate insulating film formed on a substrate, a gate electrode formed on the gate insulating film, a first insulating film pattern formed to extend from the source region to a part of a top surface of the gate electrode, and a spacer formed on a side surface of the gate electrode in a direction of the drain region.

Abstract: A mask layout for forming a semiconductor device includes an active mask pattern, a gate electrode mask pattern, a silicide blocking mask pattern, and a contact mask pattern. The active mask pattern forms source and drain regions in a substrate. The gate electrode mask pattern, disposed to overlap the active mask pattern, forms a gate electrode between the source region and the drain region. The silicide blocking mask pattern is disposed to overlap the gate electrode mask pattern and the active mask pattern in the gate electrode, the source region, and the drain regions to form a silicide blocking region. The contact mask pattern, disposed spaced apart from the silicide blocking mask pattern, forms a contact plug on the substrate. The silicide blocking mask pattern covers the gate electrode mask pattern and extends to the active mask pattern.

Abstract: A device for increasing a slew rate of a driving amplifier includes a driving amplifier, a slew rate improvement circuit, and a controller. The driving amplifier is configured to amplify an input voltage and output an output voltage. The slew rate improvement circuit is configured to provide or receive a current to increase the slew rate of the driving amplifier. The controller is configured to control an operation of the slew rate improvement circuit based on a difference between a first code corresponding to the input voltage of the driving amplifier during a current horizontal line time and a second code corresponding to the input voltage during a next horizontal line time.

Abstract: A panel control circuit for controlling a display panel comprising a first data line and a second data line includes a timing controller configured to generate input data comprising a first input data and a second input data, a first driving circuit configured to output a first video signal corresponding to the first input data into the first data line, and a second driving circuit configured to output a second video signal corresponding to the second input data into the second data line, wherein the timing controller is configured to turn off the second driving circuit based on a first deviation, a second deviation, or a third deviation.

Abstract: A switching driving circuit includes a switch configured to switch a current supplied to a target circuit, a sensing resistor connected to the switch, a controller configured to control the switch by comparing a sensing voltage applied to the sensing resistor with a reference voltage, and a compensation circuit configured to regulate the reference voltage based on an amount of variation of an input voltage input into the target circuit and an output voltage output from the target circuit.

Abstract: A method for dynamically handling the failure of the static random-access memory (SRAM) dynamic failure handling system using a cyclic redundancy check (CRC) includes obtaining a write data; determining a write address; storing the write data at the write address of a frame memory which is composed of the SRAM and includes a real address area and a spare address area which are distinguished from each other; storing, in response to the write address, a write cyclic redundancy check (CRC) generated by performing a CRC calculation on the write data; determining a read address; reading a read data from the read address of the frame memory; determining whether, based on the A CRC remainder W_CRC corresponding to the read address and the read data, a CRC error occurs, and generating an error flag when the CRC error occurs; determining a fault address based on the error flag; and mapping the fault address to one of non-fault spare addresses of the spare address area when the fault address is an address of the real a

Abstract: A switch control circuit and a switch control method are provided. In this circuit, compositions that sense a drain voltage of a switch device are added in a QR Buck Converter switch control circuit. A first resistor, a second switch, a second resistor are electrically connected to a drain terminal of a switch device to sense the 0A state of an inductor current. On the basis of a detection result, the switch control circuit turns on the switch device when an inductor current is 0A, and a drain sensing voltage (ZCD) is less than a predetermined reference voltage (REF).

Abstract: A method of seamlessly switching over between the command mode and the video mode includes receiving a command for switching over from the command mode to the video mode; generating a sampling value by measuring a time interval between a point in time of an internal synchronization signal used in the command mode and a point in time of an external synchronization signal received in the video mode; generating a parameter for shifting the internal synchronization signal based on the sampling value; shifting the internal synchronization signal to synchronize with the external synchronization signal based on the parameter; and switching over from the command mode to the video mode when the internal synchronization signal of the command mode synchronizes with the external synchronization signal. According to the disclosure, while driving a display.

Abstract: A low dropout voltage regulator includes a differential amplifier configured to output an amplified voltage by comparing a feedback voltage with a reference voltage, a pass transistor configured to receive a power input voltage into a source terminal, the amplified voltage into a gate terminal, and output an output voltage into a drain terminal, distribution resistors connected between the drain terminal and the ground terminal, configured to generate the feedback voltage, and an inrush preventer, connected in parallel between the differential amplifier and the pass transistor, and configured to output a regulated amplified voltage into the gate terminal according to a control signal, wherein the inrush preventer comprises a determiner configured to output an enable signal that is turned on during an initial driving period, and a limiter configured to output the regulated amplified voltage according to the enable signal.

Abstract: A fault handling apparatus and a fault handling method which perform a built-in self-test (BIST) and a repair on a static random-access memory (SRAM) cell, and the fault handling apparatus and the fault handling method store the fault and repair history information of a previous SRAM test, provide the information to a current test, and reflect both BIST results and the information on the previous test, thereby performing multiple repairs until there is no available spare SRAM.

Abstract: A semiconductor device includes a source region, a drain region, and a gate insulating film formed on a substrate, a gate electrode formed on the gate insulating film, a first insulating film pattern formed to extend from the source region to a part of a top surface of the gate electrode, and a spacer formed on a side surface of the gate electrode in a direction of the drain region.

Abstract: A reception device that communicates with a transmission device is provided. The reception device includes a reception circuit configured to receive a clock signal, a first data signal, and a second data signal from the transmission device, a signal synchronization circuit configured to adjust the phases of the first data signal and the second data signal, and generate a first synchronization data signal and a second synchronization data signal, a signal distribution circuit configured to adjust the phase of the clock signal and generate a first distributed clock signal and a second distributed clock signal, and adjust the phases of the first synchronization data signal and the second synchronization data signal and generate a first distributed data signal and a second distributed data signal, and an output circuit configured to process the first distributed data signal and the second distributed data signal.

Abstract: A multichip package and a method for manufacturing the same are provided. A multichip package includes: a plurality of semiconductor chips each mounted on corresponding lead frame pads; lead frames connected to the semiconductor chips by a bonding wire; and fixed frames integrally formed with at least one of the lead frame pads and configured to support the lead frame pads on a package-forming substrate.

Abstract: A slew rate acceleration circuit in a buffer circuit, is configured at least to detect a current flowing through a load stage of the buffer circuit, compare a value of the detected current with a reference value, and supply an adjusting driving voltage to an output stage of the buffer circuit based on results of the comparison for increasing a slew rate of the buffer circuit.

Abstract: A semiconductor chip packaging method includes forming a bump on a wafer, forming a coating film covering the bump, laser grooving the wafer, plasma etching the wafer on which the laser grooving is performed, exposing the bump by removing the coating film covering the bump, fabricating a semiconductor die by performing mechanical sawing of the wafer, and packaging the semiconductor die.