Abstract: A decoupling capacitor includes a first p-type metal-oxide-semiconductor (PMOS) transistor connected to a power rail in a standard cell library, a first n-type metal-oxide-semiconductor (NMOS) transistor connected to a ground rail in the standard cell library, a second PMOS transistor connected between the first NMOS transistor and the power rail, and a second NMOS transistor connected between the first PMOS transistor and the ground rail, wherein a gate of the second PMOS transistor is connected to a gate of the second NMOS transistor.

Abstract: A source driver apparatus for a display panel includes source drivers and a slew rate controller. Each of the source drivers includes a data latch, a decoder, and an output buffer. The data latch is configured to hold sub-pixel data. The decoder is configured to decode the sub-pixel data held in the data latch to provide a driving signal. The output buffer has an adjustable slew rate and is configured to buffer the driving signal to provide a buffered driving signal. The slew rate controller is configured to analyze the sub-pixel data in the data latch in each of the source drivers and dynamically control the slew rate of the output buffer in each of the source drivers.

Abstract: A semiconductor device includes a first N-type deep well region and a second N-type deep well region formed in a substrate, an N-type diffused well region formed between the first N-type deep well region and the second N-type deep well region, wherein a concentration of the N-type diffused well region is less than a concentration of the first N-type deep well region or the second N-type deep well region, a first P-type well region formed in the first N-type deep well region, a second P-type well region formed in the N-type diffused well region, an insulating film formed to be in contact with the first P-type well region, and a silicide formed on the N-type diffused well region, such that a Schottky barrier diode is formed between the silicide and the N-type diffused well.

Abstract: A display driver for driving a display panel includes a first driving circuit configured to output a first image signal to a first output pad, and a second driving circuit configured to output a second image signal to a second output pad; and the first driving circuit is further configured to output a reference image signal to the second driving circuit in response to a power down signal, and the second driving circuit is further configured to output the reference image signal output from the first driving circuit to the second output pad in response to the power down signal.

Abstract: A high voltage semiconductor device includes a semiconductor substrate, a first region, a second region, and an interconnection region. The first region includes an N-type first semiconductor region, an N-type drain region formed in the N-type first semiconductor region, a P-type first body region, an N-type source region formed in the P-type first body region, and a gate electrode formed between the N-type source region and the N-type drain region. The second region includes an N-type second semiconductor region, and a P-type second body region formed in the N-type second semiconductor region. The interconnection region is disposed between the first region and the second region, and includes a first insulation layer formed between the N-type first semiconductor region and the N-type second semiconductor region, a metal interconnection formed on the first insulation layer, and an isolation region formed in the substrate and disposed below the first insulation layer.

Abstract: A method for manufacturing a power semiconductor device includes forming a trench in a semiconductor substrate, forming a gate insulation film and a gate electrode in the trench, implanting a first conductivity type impurity into the semiconductor substrate to form a first conductivity type body region, implanting a second conductivity type impurity onto a surface of the semiconductor substrate to form a second conductivity type source region, forming an interlayer insulation film in the trench, implanting the first conductivity type impurity onto the surface of the semiconductor substrate to form a first conductivity type highly doped body contact region, exposing a portion of a side surface of the trench, and forming a source metal to be in contact with the exposed side surface of the trench.

Abstract: Provided are a low-cost semiconductor device manufacturing method and a semiconductor device made using the method. The method includes forming multiple body regions in a semiconductor substrate, forming multiple gate insulating layers and multiple gate electrodes in the body region; implementing a blanket ion implantation in an entire surface of the substrate to form a low concentration doping region (LDD region) in the body region without a mask, forming a spacer at a side wall of the gate electrode, and implementing a high concentration ion implantation to form a high concentration source region and a high concentration drain region around the LDD region. According to the examples, devices have favorable electrical characteristics and at the same time, manufacturing costs are reduced. Since, when forming high concentration source region and drain regions, tilt and rotation co-implants are applied, an LDD masking step is potentially omitted.

Abstract: A display driver IC includes a register map, an oscillator, a timing controller, an oscillator scatter, and an intellectual property (IP) block. The register map is configured to store a trim code of a fixed frequency and scatter option information. The oscillator is configured to generate an oscillator clock based on the trim code. The timing controller is configured to generate an internal synchronization signal based on the oscillator clock. The oscillator scatter is configured to output a modified trim code to the oscillator based on the trim code, the scatter option information, and the internal synchronization signal. The intellectual property (IP) block is configured to receive a modified oscillator clock generated in the oscillator based on the modified trim code.

Abstract: A semiconductor device with an embedded schottky diode and a manufacturing method thereof are provided. A semiconductor device having a schottky diode include: an epilayer of a first conductivity type, a body layer of a second conductivity type, and a source layer of the first conductivity type arranged in that order; a gate trench that extends from the source layer to a part of the epilayer; a body trench formed a predetermined distance from the gate trench and extends from the source layer to a part of the epilayer; and a guard ring of the second conductivity type that contacts an outer wall of the body trench and formed in the epilayer.

Abstract: A display driver semiconductor device includes a high voltage well region formed on a substrate, a first semiconductor device, a second semiconductor device, and a third semiconductor device. The first semiconductor device is formed on the high voltage well region and includes a first gate insulating layer formed using a deposition process. The second semiconductor device is formed adjacent to the first semiconductor device and includes a second gate insulating layer formed using a thermal process. The third semiconductor device is formed adjacent to the second semiconductor device and includes a third gate insulating layer.

Abstract: A semiconductor device includes a substrate including a first region and a second region, a first transistor and a second transistor formed in the first region and second region, respectively, wherein the first transistor includes a thick gate insulating layer and a thin buffer insulating layer formed in the substrate, a first gate electrode formed on the thick gate insulating layer, a first spacer formed on the thin buffer insulating layer, and a source region and a drain region formed in the substrate.

Abstract: A wafer-level chip-scale package includes: a power semiconductor comprising a first semiconductor device formed on a semiconductor substrate, and a second semiconductor device formed on the semiconductor substrate; a common drain electrode connected to the first semiconductor device and the second semiconductor device; a first source metal bump formed on a surface of the first semiconductor device; and a second source metal bump formed on the surface of the second semiconductor device; wherein the first source metal bump, the common drain electrode, and the second source metal bump form a current path in an order of the first source metal bump, the common drain electrode, and the second source metal bump.

Abstract: A decoder of a display apparatus and a decoding method thereof is provided. The decoder comprises a first switching control block configured to select at least two section values from a plurality of gamma gray level values based on predetermined low bits of inputted data, and a second switching control block configured to select section values from the at least two selected section values based on predetermined high bits of the data and output at least two channel values.

Abstract: A semiconductor device includes a first N-type deep well region and a second N-type deep well region formed in a substrate, an N-type diffused well region formed between the first N-type deep well region and the second N-type deep well region, wherein a concentration of the N-type diffused well region is less than a concentration of the first N-type deep well region or the second N-type deep well region, a first P-type well region formed in the first N-type deep well region, a second P-type well region formed in the N-type diffused well region, an insulating film formed to be in contact with the first P-type well region, and a silicide formed on the N-type diffused well region, such that a Schottky barrier diode is formed between the silicide and the N-type diffused well.

Abstract: A power semiconductor device includes a drain region and a source region disposed on a substrate, a gate insulating layer and a gate electrode disposed on the substrate and disposed between the drain region and the source region, a protection layer in contact with a top surface of the substrate and a top surface of the gate electrode, a source contact plug connected to the source region, a drain contact plug connected to the drain region, and a field plate plug in contact with the protection layer, wherein a width of the field plate plug is greater than a width of the source contact plug or a width of the drain contact plug.

Abstract: A display driving device for driving a display panel includes a first driving circuit configured to output a first image signal, a second driving circuit configured to output a second image signal, a first switch circuit connected to the first driving circuit, and configured to transmit the first image signal to a part of a first set of sub-pixels arranged in the display panel based on a first switching signal during a first horizontal time interval, and a second switch circuit connected to the second driving circuit, and configured to transmit the second image signal to a part of a second set of sub-pixels arranged in the display panel adjacent to the first set of sub-pixels based on a second switching signal during the first horizontal time interval, wherein a width of the first switching signal and a width of the second switching signal in the first horizontal time differ from each other.

Abstract: A power switch circuit comprises a first level shifter configured to turn on a first switching element configured to receive a supply voltage from an external voltage supply pad in response to a program operation of a one-time programmable (OTP) memory cell array, a second level shifter configured to turn on a second switching element and provide the supply voltage to the OTP memory cell array in response to the program operation, a third level shifter configured to turn on a third switching element and provide an internally generated power voltage to the OTP memory cell array in response to a read operation of the OTP memory cell array, and an Electro-Static Discharge (ESD) protection circuit configured to turn off the first switching element in response to a flow of ESD voltage from the voltage supply pad.

Abstract: Provided are a semiconductor device, a method of manufacturing the same, and a method of forming a uniform doping concentration of each semiconductor device when manufacturing a plurality of semiconductor devices. When a concentration balance is disrupted due to an increase in doping region size, doping concentration is still controllable by using ion blocking patterns to provide a semiconductor device with uniform doping concentration and a higher breakdown voltage obtainable as a result of such doping.

Abstract: A semiconductor package manufacturing method includes preparing a flexible film including input wire patterns and output wire patterns, preparing a semiconductor chip including metal bumps, attaching the semiconductor chip to one side of the flexible film, such that the metal bumps are connected to either one or both of the input wire patterns and the output wire patterns, and attaching a first absorbing and shielding tape to another side of the flexible film, wherein the first absorbing and shielding tape includes an absorption film and a protective insulating film disposed on the absorption film.

Abstract: A control buffer in a source driver includes a first CMOS inverter configured to output a switch signal to control turning on and off of a switch, and a first tri-state inverter that is connected to the first CMOS inverter and configured to selectively adjust a size of the control buffer, wherein a slew rate of the switch signal is adjusted depending on the size of the control buffer.