Abstract: Embodiments of the present invention relate to multiple parallel lookups using a pool of shared memories by proper configuration of interconnection networks. The number of shared memories reserved for each lookup is reconfigurable based on the memory capacity needed by that lookup. The shared memories are grouped into homogeneous tiles. Each lookup is allocated a set of tiles based on the memory capacity needed by that lookup. The tiles allocated for each lookup do not overlap with other lookups such that all lookups can be performed in parallel without collision. Each lookup is reconfigurable to be either hash-based or direct-access. The interconnection networks are programmed based on how the tiles are allocated for each lookup.

Abstract: The present disclosure describes aspects of a sub-device field-effect transistor architecture for integrated circuits. In some aspects, an integrated field-effect transistor (FET) is implemented with multiple FET sub-devices. During operation, source-side FET sub-devices of the integrated FET may operate in the linear region instead of in saturation. Operating in the linear region, the source-side FET sub-devices of the integrated FET may exhibit less threshold voltage or current sensitivity than other drain-side FET sub-devices that operate in saturation. A device layout of the integrated FET may be designed such that the less sensitive source-side FET sub-devices surround or protect the other more sensitive drain-side FET sub-devices from random variations or density issues at edges of the device layout. By so doing, a threshold voltage or current sensitivity of the integrated FET may be reduced, resulting in improved matching between integrated FET devices.

Abstract: A method for managing an observed order of instructions in a computing system includes utilizing an overloaded memory barrier instruction to specify whether a global ordering constraint or a local ordering constraint is enforced.

Abstract: A circuit and corresponding method for dynamic voltage frequency scaling (DVFS) on a chip employ a delay-locked loop (DLL)-based clocking architecture. The circuit comprises a DLL including a fixed delay line path, with a first insertion delay, and variable delay line path, with a second insertion delay, and a clock generator. The clock generator is configured to source a DLL input clock to the fixed and variable delay line paths at a start-up frequency prior to a run-time frequency. The start-up frequency is lower relative to a target frequency for the chip. The run-time frequency is configured based on DVFS, following release of the chip from reset. The chip is configured to be released from reset with the DLL locked at the start-up frequency, enabling the second insertion delay to match the first insertion delay with the DLL locked at the start-up frequency.

Abstract: In an embodiment, a method comprises: forming a fin feature on a portion of a surface of a substrate; forming a first region of polycrystalline silicon over a first portion of the fin feature; forming a second region of polycrystalline silicon over a second portion of the fin feature; forming a third region of polycrystalline silicon over a third portion of the fin feature, wherein the third region of polycrystalline silicon is disposed between (i) the first region and (ii) the second region; forming a first spacer region between the first region and the third region; forming a second spacer region between the second region and the third region; removing the third region and at least a portion of the fin feature formed under the third region to thereby form a gap; and disposing a second dielectric material into the gap to form an isolation component.

Abstract: The present disclosure describes aspects of constant-density writing for magnetic storage media. In some aspects, a constant-density writer delays transitions between bits within write data to enable constant-density writing. The write data has an initial bit period based on a constant clock signal, which is generated based on the rotation of a media disk. The constant-density writer modifies the write data to generate phase-delayed write data, which has a bit period that is greater than or equal to the initial bit period. To realize this bit period, the constant-density writer changes write phases of bit transitions within the write data. The constant-density writer can also insert stretch bits, filter single-bit transitions, and mitigate glitches within the phase-delayed write data.

Abstract: A method for communication over a wireless interface between transceivers that are moving with respect to each other. The method includes transmitting, by a communication station (STA) in a moving vehicle over a wireless channel to a receiver outside the vehicle, a sequence of data symbols encoded in accordance with a frequency-domain multiplexing scheme extending over a range of sub-carrier tones. A condition affecting the wireless channel is evaluated. Responsively to the evaluated condition, a pilot scheme is selected from among a plurality of available pilot schemes, for interleaving of pilot signals in specified sub-carrier tones of the data symbols. An indication of the selected pilot scheme is exchanged between the STA and the receiver. The pilot signals are interleaved in the transmitted data symbols in accordance with the selected pilot scheme.

Abstract: A networking system includes a transmitter, a waveguide and a receiver. The transmitter is configured to generate a millimeter-wave signal carrying data. The waveguide is transmissive at millimeter-wave frequencies and is configured to receive the millimeter-wave signal from the transmitter, and to guide the millimeter-wave signal from the transmitter to a downstream location by having a dielectric constant that varies over a transversal cross-section of the waveguide in accordance with a predefined profile. The receiver is configured to receive the millimeter-wave signal guided by the waveguide, and to extract the data carried by the received millimeter-wave signal.

Abstract: A Serializer/Deserializer (SERDES) circuit is disclosed. The circuit includes an input/output (I/O) pad for coupling to a dual duplex SerDes link. A transmit circuit is coupled to the I/O pad, and includes transmit rate selection circuitry to select between data transmission at a full rate or a sub-rate. A receive circuit is coupled to the I/O pad, and includes receive rate selection circuitry to select between data receipt at the full rate or the sub-rate. Data transmitted by the transmit circuit is at a data rate different than data received by the receive circuit.

Abstract: An example embodiment combines use of a branch predictor with cache-like storage of previously executed branch targets to improve processor performance while minimizing hardware cost. The branch predictor is configured to predict both conditional branch and indirect branch targets and includes a combined predictor table configured to store at least one tagged conditional branch prediction in combination with at least one tagged indirect branch target prediction. The at least one tagged indirect branch target prediction is configured to include a predicted partial target address of a complete target address, the complete target address associated with an indirect branch instruction of a processor. The predictor includes prediction logic configured to use the predicted partial target address to produce a predicted complete target address of the complete target address for use by the processor prior to execution of the indirect branch instruction.

Abstract: Monolithic three-dimensional integration can achieve higher device density compared to 3D integration using through-silicon vias. A test solution for M3D integrated circuits (ICs) is based on dedicated test layers inserted between functional layers. A structure includes a first functional layer having first functional components of the IC with first test scan chains and a second functional layer having second functional components of the IC with second test scan chains. A dedicated test layer is located between the first functional layer and the second functional layer. The test layer includes an interface register controlling signals from a testing module to one of the first test scan chains and the second test scan chains, and an instruction register connected to the interface register. The instruction register processes testing instructions from the testing module. Inter-layer vias connect the first functional components, the second functional components, and the testing module through the test layer.

Abstract: Embodiments described herein provide a method for accessing a host memory through non-volatile memory over fabric bridging with direct target access. A first memory access command encapsulated in a first network packet is received at a memory interface unit and from a remote direct memory access (RDMA) interface and via a network fabric. The first memory access command is compliant with a first non-volatile memory interface protocol and the first network packet is compliant with a second non-volatile memory interface protocol. The first network packet is unwrapped to obtain the first memory access command. The first memory access command is stored in a work queue using address bits of the work queue as a pre-set index of the first memory access command. The first memory access command is sent from the work queue based on the pre-set index to activate a first target storage device.

Abstract: A voltage-mode digital-to-analog converter (DAC) includes multiple bit processing circuits to generate an output voltage responsive to a binary input. Each of the multiple bit processing circuits includes a first switch circuit and a second switch circuit. The first switch circuit is to selectively couple one of multiple reference voltages to a first output load in response to receiving a first input bit during a first bit time. The first output load has a value proportional to d. The second switch circuit is to selectively couple one of the multiple reference voltages to a second output load in response to receiving a second input bit during a second bit time. The second output load has a value corresponding to the first output load. The first and second output loads are disposed in parallel, and serially couple to a third output load having a value proportional to (1-d).

Abstract: A first communication device generates a first portion and a second portion of a wakeup radio (WUR) wakeup packet. The first portion of the WUR wakeup packet corresponds to a wireless local area network (WLAN) legacy preamble, and spans a first frequency bandwidth. The second portion of the WUR wakeup packet spans a second bandwidth that is less than the first bandwidth, and is configured to cause a WUR of a second communication device to cause a WLAN network interface device of the second communication device to transition from a low power state to the active state. Generating the second portion of the WUR wakeup packet includes i) generating a sync portion having a plurality of sync symbols, and ii) generating a wakeup packet body. The first communication device transmits the WUR wakeup packet.

Abstract: A first communication device transmits a first communication frame that includes scheduling information corresponding to a time period in which an uplink multi-user transmission is to occur. The scheduling information indicates a start time of the time period. The first communication frame includes an indication of a group of two or more second communication devices that are to transmit simultaneously during the time period as part of the uplink multi-user transmission. The first communication device transmits a second communication frame during the time period. The second communication frame is configured to trigger at least some second communication device in the group of two or more second communication devices to transmit simultaneously as part of the uplink multi-user transmission. The first communication device receives the uplink multi-user transmission during the time period, the uplink multi-user transmission being responsive to the second communication frame.

Abstract: Systems, methods, and other embodiments associated with validating de-authentication requests to prevent spoofing are described. According to one embodiment, an apparatus includes a wireless controller configured to receive a de-authentication request and determine whether the de-authentication request is invalid based on the wireless controller's receipt of two or more responses to a timing request sent by the wireless controller. Only one response is expected. The two or more responses include the address of a first station.

Abstract: A bias circuit comprises a closed loop gain stage arranged to determine a difference between a first current in a first branch circuit and a second current in a second branch circuit, where the first branch circuit and second branch circuit are coupled to respective terminals of a magnetic resistor (MR). A first set of current mirrors is arranged to provide a source current to the first terminal of the MR and the second set of current mirrors is arranged to provide a sink current to the second terminal of the MR. The first set of current mirrors and a second set of current mirrors are balanced to reduce a difference in setting time between the source current and sink current. The source current and sink current further reduce the difference between the first current and the second current to provide a constant voltage bias to the MR based on a voltage of a voltage source.

Abstract: A method of operation for an Ethernet transceiver is disclosed. The method includes entering a fast retrain sequence of steps. The fast retrain sequence of steps includes transferring two-level symbols to a link partner; and directly following transferring of the two-level symbols, transferring multi-level symbols to the link partner, the multi-level symbols having greater than two symbol levels.

Abstract: A first communication device includes a first timer and a second communication device includes a second timer. The first communication device receives, from the second communication device, a packet that includes a timestamp that corresponds to a least significant portion of the second timer. The first communication device determines whether a most significant bit of a least significant portion of the first timer is different than a most significant bit of the timestamp. At least when the most significant bit of the least significant portion of the first timer is different than the most significant bit of the timestamp: the first communication device determines a mathematical difference between i) the least significant portion of the first timer and ii) the timestamp, and selectively adjusts a most significant portion of the first timer based on the mathematical difference. The first communication device uses the timestamp to set the least significant portion of the first timer.

Abstract: A first communication device generates a media access control (MAC) frame that includes an indication of a change in a block acknowledgment (BA) session that was previously established between the first communication device and a second communication device. The first communication device transmits the MAC frame to the second communication device. The MAC frame is configured to cause the second communication device to adopt the change in the BA session in response to receiving the MAC frame.