Abstract: Systems, methods, and other embodiments associated with paging auto-acknowledgement are described. According to one embodiment, a method for performing paging auto-acknowledgement includes transmitting according to a protocol, on a first channel, a synchronization packet to a slave device, where the synchronization packet specifies a second channel on which a subsequent packet will be transmitted to the slave device. The protocol specifies that the slave device send an acknowledgement to the synchronization packet on the first channel prior to switching to the second channel. The method includes, when predetermined automatic acknowledgement criteria are met, transmitting the subsequent packet to the slave device on the second channel in the absence of an acknowledgement to the synchronization packet from the slave device.

Abstract: Chip packages with improved tamper resistance and methods of using such chip packages to provide improved tamper resistance. A lead frame includes a die attach paddle, a plurality of outer lead fingers, and a plurality of inner lead fingers located between the outer lead fingers and the die attach paddle. A chip is attached to the die attach paddle. The chip includes a surface having an outer boundary and a plurality of bond pads arranged proximate to the outer boundary. A first plurality of wires extend from the outer lead fingers to respective locations on the surface of the chip that are interior of the outer boundary relative to the bond pads. A tamper detection circuit is coupled with the first plurality of wires. A second plurality of wires extend from the inner lead fingers to the bond pads on the chip. The second plurality of wires are located between the lead frame and the first plurality of wires.

Abstract: A network device receives a packet having i) a first field that is to be updated by the network device, and ii) a second field that includes current error detection information corresponding to content of the packet, the content including the first field. The network device determines an update value that is to be added to a current value of the first field to generate a new value of the first field. The network device generates new error detection information using the current error detection information and the update value, and without using the current value of the first field. The network device modifies the second field to include the new error detection information, and modifies the first field to include the new value.

Abstract: A master integrated circuit (IC) chip includes transmit circuitry and receiver circuitry. The transmit circuitry includes a timing signal generation circuit to generate a first timing signal, and a driver to transmit first data in response to the first timing signal. A timing signal path routes the first timing signal in a source synchronous manner with the first data. The receiver circuitry includes a receiver to receive second data from a slave IC chip, and sampling circuitry to sample the second data in response to a second timing signal that is derived from the first timing signal.

Abstract: A new approach is proposed that contemplates systems and methods to support virtio-based data packet path optimization for live virtual machine (VM) migration for Linux. Specifically, a data packet receiving (Rx) path and a data packet transmitting (Tx) path between a VM running on a host and a virtual function (VF) driver configured to interact with a physical network device of the host to receive and transmit communications dedicated to the VM are both optimized to implement a zero-copy solution to reduce overheads in packet processing. Under the proposed approach, the data packet Tx path utilizes a zero-copy mechanism provided by Linux kernel to avoid copying from virtio memory rings/Tx vrings in memory of the VM. The data packet Rx path also implements a zero-copy solution, which allows a virtio device of the VM to communicate directly with the VF driver of the network device while bypassing a macvtap driver entirely from the data packet Rx path.

Abstract: A probe card for testing dies of a substrate during a wafer sort process includes a printed circuit board (PCB) and a test site arranged to connect respectively to one of the dies during a test cycle. The test site includes a first pin connecting band and a first pin set. The first pin connecting band is connected to the PCB. The first pin set is connected to the first pin connecting band and includes a pin configuration for a testing device to perform a first type of test on a first die. The test site includes only pins in the first pin set. A number of pins in the first pin set is less than a number of pins used to perform a second type of test on the first die. The second type of test is performed at a slower processing speed than the first type of test.

Abstract: A method, performed at a first communication device, for transmitting a physical layer (PHY) protocol data unit (PPDU) is described. An initiating PPDU is received from a second communication device. The initiating PPDU has a PHY header that indicates a first PPDU format of the initiating PPDU and a PPDU format field that indicates a second PPDU format of a responding PPDU to be transmitted in response to the initiating PPDU. The responding PPDU is generated using the second PPDU format. The responding PPDU is transmitted in response to the initiating PPDU.

Abstract: In a method for egress processing packets in a network device, a first stage engine, implemented in hardware, identifies a particular set of computer-readable instructions for a particular packet. The particular set of computer-readable instructions is identified from among a plurality of sets of computer-readable instructions stored in a memory, respective ones of the plurality of sets of computer-readable instructions being for performing different sets of egress processing operations with respect to different packets. A second stage processor, configured to execute computer-readable instructions stored in the memory, executes the particular set of computer-readable instructions, identified by the first stage engine, to perform the corresponding set of egress processing with respect to the particular packet.

Abstract: Methods and apparatus for transmitting Ethernet data along an Ethernet link with a BASE-T transceiver are disclosed. One exemplary BASE-T Ethernet transceiver includes an Ethernet data framing module having an input interface to receive Ethernet block data bits at a first data rate. Logic associates the Ethernet block data bits with an auxiliary bit and a number of zero bits. An error encoder is coupled to the logic to encode all of the data bits, auxiliary bit and zero bits into an error encoded transport frame having plural error check bits. A symbol mapper receives the error encoded transport frame and transforms the error encoded transport frame into multiple symbols. A transmitter coupled to the symbol mapper transmits the multiple symbols over an Ethernet link at one of a selection of symbol rates. The data rate of data transmitted over the Ethernet link is based on the number of zero bits.

Abstract: A method of determining whether a wireless communication medium is clear is carried out on a client device, and includes: associating with a first virtual access point (AP) of a plurality of virtual APs implemented by a physical AP; receiving, from a physical AP, a message identifying the basic service set (BSS) color of each of the plurality of virtual APs implemented by on the physical AP; detecting a packet data unit; measuring the energy of the packet data unit; decoding a BSS color from the packet data unit; if the decoded BSS color is the same as a BSS color in the message from the physical AP, then setting an energy threshold to a first level; if the decoded BSS color is not the same as any BSS color in the message from the physical AP, then setting an energy threshold to a second level, wherein the second level is higher than the first level; and transmitting or refraining from transmitting a packet data unit based on a comparison of the measured energy and the energy threshold.

Abstract: A circuit system and process utilizes back electromotive force (BEMF) voltage to assist in safe power down of devices, such as the read/write head in from low factor disk drives or similar devices. The BEMF voltage from a motor device, such as a spindle motor utilized in a circuit using negative voltage to drive some switches, such as positive channel metal oxide semiconductor (“PMOS”) driver transistors, to reduce and/or effectively minimize the on-resistance of the switches while delivering the current from BEMF voltage of the motor to another device, such as a motor that retracts controls a read/write head.