Abstract: A system including a receiving module to receive data from cells of memory, each cell storing multiple bits, each bit corresponding to a different type of page of the memory, the bits stored in a cell denoting a state of the cell, and the data including bits from a page of the memory or states of cells along a word line of the memory. A processor generates a reliability indication for a first portion of the data corresponding to a first cell based on the first portion of the data and one or more second portions of the data corresponding to one or more of the cells that are adjacent to the first cell. A decoder decodes the first portion of the data based on the first portion of the data and the reliability indication for the first portion of the data.

Abstract: Aspects of the disclosure provide a circuit having an amplifier and a load current based control circuit. The amplifier is configured to detect a difference between a feedback voltage and a reference voltage, and control, based on the difference, a pass device to regulate an output voltage for supplying power to load devices. The feedback voltage is indicative of the regulated output voltage from the pass device. The load current based control circuit is configured to sense a load current output from the pass device to the load devices and generate a control signal to adjust a compensation capacitance based on the sensed load current to adjust a zero frequency of the circuit.

Abstract: Systems, methods, and other embodiments are described that are associated with selective shorting of clock branches. In one embodiment, an apparatus includes a selective shorting device connected between a first clock branch that conducts a slow clock signal having a first frequency and a second clock branch that conducts a fast clock signal having a second frequency that is an integer multiple of the first frequency. The selective shorting device is configured to electrically connect and disconnect the first clock branch and the second clock branch. The selective shorting control mechanism is configured to control the selective shorting device to electrically connect the clock branches during a controlling portion of the slow clock signal.

Abstract: Systems and methods for improving the performance of iterative decoders on various channels with memory are disclosed. These systems and methods may reduce the frequency or number of situations in which the iterative decoder cannot produce decoded data that matches the data that was originally sent in a communications or data storage system. The iterative decoder includes a SISO channel detector and an ECC decoder and decodes the coded information according to at least one iterative decoding algorithm in regular decoding mode and/or at least one iterative decoding algorithm in error-recovery mode.

Abstract: Systems and methods for reducing noise from an input signal are provided. An input signal is received. The input signal is transformed from a time domain to a plurality of subbands in a frequency domain, where each subband of the plurality of subbands includes a speech component and a noise component. For each of the subbands, an amplitude of the speech component is estimated based on an amplitude of the subband and an estimate of at least one signal-to-noise ratio (SNR) of the subband. The estimating of the amplitude of the speech component is based on a closed-form solution. The plurality of subbands in the frequency domain are filtered based on the amplitudes of the speech components.

Abstract: System and methods are provided for processing composite video signals. The system includes: a clock synthesizer configured to generate a line lock clock signal; an interpolation unit configured to generate source data associated with a source composite video signal, the source composite video signal being related to a source clock signal; a buffer unit configured to store the source data based at least in part on the source clock signal and provide destination data based at least in part on the line lock clock signal; a signal processing unit configured to process the destination data to extract a synchronization component and determine a phase error between the synchronization component and the line lock clock signal. The clock synthesizer is further configured to adjust the line lock clock signal based at least in part on the phase error.

Abstract: A micro-milliactuator, a micro-microactuator, an actuator arm assembly, a hard disk drive and a method for operation of the hard disk are provided. In accordance with one aspect, the actuator arm assembly includes an arm, a slider for reading and writing information to disk media in response to read/write signals, and an actuator selected from the group comprising a micro-milliactuator and a micro-microactuator. The actuator has the slider mounted thereon and supports it above the disk media. The actuator includes one or more piezoelectric actuators for horizontally shifting the slider in response to actuator control signals. The actuator further includes one or more sensors physically coupled thereto for vibration sensing, compensation and suppression, the one or more sensors generating sensor signals in response to sensed vibrations during operation, wherein the actuator control signals are generated at least partially in response to the sensor signals.

Abstract: System and methods are provided for integrated circuit design. An initial layout including first circuit units is generated, at least part of the first circuit units obtaining power from a first power supply structure. Second circuit units that obtain power from a second power supply structure are determined, the second circuit units being included in the first circuit units. The second circuit units are grouped. The grouped second circuit units are connected to form one or more grids. The one or more grids are connected to the second power supply structure.

Abstract: Systems, methods, and other embodiments associated with improving communication latencies by using a hardware linked list are described. According to one embodiment, an apparatus includes a pointer memory configured to store a free list that includes a plurality of pointers that each point to an address in a memory that is unallocated. The apparatus includes a memory controller configured to manage a linked list using pointers from the plurality of pointers stored in the free list. The apparatus includes a list memory configured to store the linked list.

Abstract: A method includes generating a first subset of codeword symbols by processing, during each of a plurality of iterations, a first input and a second input. The first input is a function of (i) an output, during a respective one of the plurality of iterations, of a last processing stage of a first plurality of processing stages and (ii) a symbol, of a first subset of original symbols, corresponding to the respective iteration. The second input is a function of (i) an output, during the respective iteration, of a last processing stage of the second plurality of processing stages and (ii) a symbol, of a second subset of original symbols, corresponding to the respective iteration. The method also includes generating a second subset of codeword symbols by processing, during each of the plurality of iterations, the first input and the second input.

Abstract: A method of encoding an input data into a codeword that satisfy a k constraint includes partitioning the input data into a plurality of data blocks comprising a first data block and a plurality of remaining data blocks; performing a first analysis of the plurality of data blocks for modifying each of the plurality of remaining data blocks that satisfy a first predetermined criterion; performing a second analysis of the plurality of data blocks after the first analysis for modifying each of the plurality of data blocks that satisfy a second predetermined criterion; and converting each bit of the plurality of data blocks after the second analysis to produce the codeword in Non-Return-to-Zero (NRZ) format with the k constraint. There is also provided a method of decoding the codeword with satisfies the k constraint into an output data, and the corresponding encoder and decoder.

Abstract: Some of the embodiments of the present disclosure provide a method comprising: storing volatile data in nonvolatile memory; over a time interval, periodically refreshing the volatile data by (i) reading the volatile data from the nonvolatile memory and (ii) rewriting the volatile data to the nonvolatile memory; determining a number of errors in the volatile data that is read during the periodic refresh of the volatile data; and based, at least in part, on the number of errors that is determined, modifying the time interval. The method may also comprise decreasing the time interval if the number of errors is determined to be greater than an error threshold value.

Abstract: A radio-frequency amplifier includes a matching network comprising a switching unit. The switching unit is operable in a first condition to provide a selected impedance at a first selected frequency. The switching unit is operable in a second condition to form a bandstop filter. A stop band of the bandstop filter includes a second selected frequency. The first selected frequency may be a second harmonic of a transmission frequency different from the second selected frequency. A multi-band transceiver is also described, as is a method of transmitting a first signal and a second signal.

Abstract: A system including a circuit to compensate for sampling phase jitter. The system includes a channel estimator to determine, based on training symbols in a preamble of a data packet received via a communication channel, an estimate of the communication channel and a carrier frequency associated with the communication channel. The circuit compensates, based on the determined carrier frequency, a phase of the estimate of the communication channel to adjust for a carrier frequency offset associated with the communication channel, and, based on a data rate at which the data packet was received via the communication channel, selectively compensates the estimate of the communication channel for sampling phase jitter.

Abstract: Systems and methods are provided for processing a computing task divided into a plurality of discrete tasks using a plurality of data processors. The system includes a system memory having memory space for storing results from processed discrete tasks. The system further includes a plurality of data processors of differing types, a first data processor writing results to the system memory in a first format that is different from a second format that a second data processor uses to write results to the system memory. Further, a scheduler is configured to assign a first set of discrete tasks to the first data processor and a second set of discrete tasks to the second data processor so that a results writing conflict where the second data processor writes results to the system memory that overwrite results written to the system memory by the first data processor is avoided.

Abstract: A memory controller comprises a memory controller core that receives packets of data and generates memory transactions for each of the packets of data. A memory interface transmits each of the memory transactions to one of a plurality of memory banks of a memory. The memory controller directs each of the memory transactions to a different memory bank than an immediately preceding memory transaction.

Abstract: A first communication device receives a non-sounding data unit from a second communication device that does not support beamforming training procedures. The first communication device develops an estimate of a reverse channel via which the non-sounding data unit traveled based on the non-sounding data unit. The first communication device develops a transmit beamforming matrix based on the estimate of the reverse channel, the transmit beamforming matrix for the first communication device to utilize when transmitting via a forward channel.

Abstract: An integrated circuit includes a generator. The generator, based on a summation signal, generates a clock signal having a frequency. Multiple devices generate respective requests. Each of the requests requests transfer of data on a bus. Each of the devices is configured to, based on the frequency of the clock signal, transfer the data for the corresponding request on the bus. A summer receives the requests and based on a number of the requests being in an asserted state during a first period of time, generates the summation signal. A first module, based on the summation signal, increases a second period of time that a first request is in an asserted state. The second period of time is increased to include or overlap the first period of time. The summer, as a result of the increase, generates the summation signal further based on the first request.

Abstract: A filter expression is received at a wireless device assembly of a communication device. While a host assembly of the communication device is in a sleep mode, the wireless device assembly receives a signal having packet data, and determines whether the packet data contains a data pattern indicated by the filter expression. If the packet data contains the data pattern, the wireless device assembly communicates a wakeup signal to the host assembly for changing the host assembly from the sleep mode to an active mode. If the packet data does not contain the data pattern, the wireless device assembly does not communicate the wakeup signal to the host assembly.

Abstract: Receiving devices and methods for suppressing interference from a data signal received at a receiving device are provided. The receiving device has m receive antennas. A training signal set transmitted from a first transmitting device is received at the receiving device. The training signal set includes (i) data for each transmit antenna of n transmit antennas included on the first transmitting device and (ii) information sufficient to determine a channel estimate corresponding to a communication channel between the first transmitting device and the receiving device. The channel estimate is determined based on the training signal set. The channel estimate includes an m-by-n description of the communication channel. The data signal received at the receiving device is filtered based on the channel estimate to suppress the interference in the data signal. The data signal is transmitted from a second transmitting device different from the first transmitting device.