Abstract: The present disclosure includes apparatus, systems, and techniques relating to noise-predictive detector adaptation. A described technique includes operating a decoder to decode a received encoded signal based on estimation parameters to produce paths including a first path and a second path, the second path being an alternate to the first path, determining a decoded path based on at least a portion of the paths, determining a winning path of the first path and the second path based on whether the decoded path matches the first path or the second path, and updating the estimation parameters based on one or more error terms and the winning path to favor selection of the winning path by the decoder and to disfavor selection of a losing path of the first and second paths by the decoder in a subsequent iteration.

Abstract: System and methods are provided for data storage management in a memory device. A first logical block corresponding to a plurality of first physical blocks of a memory device is selected. A source physical block within the first physical blocks is determined, the source physical block including less valid data than one or more second physical blocks within the first physical blocks. A target physical block of the memory device is obtained. The valid data in the source physical block is copied to the target physical block. The source physical block is released for storing new data.

Abstract: In nonbinary iterative decoding, a data recovery scheme corrects for corrupted or defective data by determining reliability metrics for blocks of decoded nonbinary data. Block or windowed detectors generate block reliability metrics for data blocks (rather than individual bits) of decoded data using soft information from the regular decoding mode or from new iterative decoding iterations performed during defect detection mode. A defect detection system triggers corrective decoding of selected data blocks based on the block reliability metrics, by for example, comparing the block reliability metrics to a threshold or by selecting an adjustable number of the least reliable data blocks.

Abstract: In one embodiment, a circuit couples an integrated circuit to a powerline and protects the integrated circuit from overvoltage noise. In one example, the integrated circuit comprises a two-port differential transceiver. Respective Schottky diodes couple the ports to a power supply and reference, so one diode for each port conducts current in forward bias if an applied voltage exceeds a respective voltage reference plus the forward voltage of that diode. A respective end of a first transformer winding feeds each input port. Respective ends of a second transformer winding couple to capacitors that couple with the powerline. Back-to-back zener diodes are connected between the ends of the second winding. A zener diode with a breakdown voltage set based on the power supply voltage plus a margin is coupled between the power supply and ground so that the power supply voltage does not exceed a desired value plus the margin.

Abstract: A pulse width modulation technique is disclosed for use in an image forming device such as a laser printer or a photocopier. The technique implements a pacer to synthesize the frequency of a serializer circuit by stretching (or shrinking) pixel pulse train data. The pacer stretches the pixel pulse train data in accord with increment data that is based upon information about the image forming device, such as the number of bits in the pixel pulse train data, the number of bits in print engine pulse train, the target print engine frequency, and the serializer frequency. The technique can be implemented with digital circuits that provide digital test data.

Abstract: Systems, methods, and other embodiments associated with controlling a clocking rate of a processor clock are described. According to one embodiment, an apparatus includes a register, a selector, and a clock gate. The register stores a set of bits arranged in a clocking pattern. In response to receiving an edge of a first clock signal, the selector selects a bit of the set of bits in the register. With each edge of the first clock signal, the selector selects a next bit in the clocking pattern. The clock gate implements a conjunction of the selected bit and the edge. The clock gate then outputs the conjunction of the selected bit and the edge as a second clock signal.

Abstract: A network device activates an alternative path flow control for spanning tree protocol. The network device includes a receiver that receives first network traffic from a first transmitter of the first network traffic, the first network traffic being destined for a first receiver along a first network path, and receives second network traffic from the first receiver, the second network traffic being destined for at least the first transmitter along a second network path. The network device also has a pause frame detector configured to detect in the second network traffic a pause frame for controlling a flow of the first network traffic. The network device, furthermore, has an alternative network path activator configured to activate, a third network path that is different from the first network path, for transmitting the first network traffic to the first receiver.

Abstract: Embodiments include a method comprising: receiving a signal comprising a plurality of symbols; estimating that a first symbol of the plurality of symbols has a first value; based on the first value of the first symbol, cancelling, at least in part, inter symbol interference that the first symbol has on a second symbol of the plurality of symbols; determining a first error associated with the first value of the first symbol; and in response to the first error being higher than a threshold value, generating, for the first symbol, a second value that is different from the first value of the first symbol, and based on the second value of the first symbol, cancelling, at least in part, inter symbol interference that the first symbol has on the second symbol.

Abstract: Aspects of the disclosure provide a method. The method includes regulating a time for turning on a switch to transfer energy via a transformer in a first control mode, determining a turn-on time for a second control mode based on the regulated time in the first control mode, and controlling the switch based on the determined turn-on time in the second control mode to transfer energy via the transformer.

Abstract: A method that includes coupling a first device to a client device using a universal serial bus (USB) link, and detecting, by the first device, a USB operating system (OS) descriptor request made by the client device. The method further includes reporting, by the first device, a mass storage interface to the client device in response to a detected USB OS descriptor request, and using the mass storage interface to install, in the client device, a device driver associated with the first device.

Abstract: Embodiments of the present invention provide a method that comprises, within a sample window, determining an active time of a central processing unit (CPU) at an operating frequency. If there are any different operating frequencies within the sample window, the method further comprises determining active times of the CPU at the different operating frequencies within the sample window and, based upon the active times for the operating frequencies within the sample window, calculating a millions of instructions per second (MIPS) value for the sample window. The method further comprises performing a comparison of the MIPS value to a threshold value and, based upon the comparison of the MIPS value to the threshold value, setting an operating frequency of the CPU for a next sample window.

Abstract: A wireless device for wireless communication in a wireless area network. The wireless device includes a main radio channel for exchanging data with an access point in the wireless area network, as well as an auxiliary radio channel for scanning for availability of other access points in the wireless area network.

Abstract: Systems and techniques relating to wireless communications are described. A described technique includes determining a first frequency offset based on a received preamble of a wireless communication signal and a known preamble, the received preamble having been generated based on a spreading sequence and the known preamble, determining a second frequency offset based on the received preamble and the known preamble, and processing at least a portion of the wireless communication signal based on the first frequency offset and the second frequency offset. Determining the first frequency offset can include performing a multi-chip-level differential frequency offset acquisition that uses two or more chips associated with the received preamble. Determining the second frequency offset can include performing a symbol-level differential frequency offset acquisition that uses two or more symbols associated with the received preamble, where each of the two or more symbols are encoded by two or more chips.

Abstract: An FM audio receiver can include a mono/stereo detector that causes the audio receiver to output either a monophonic or a stereophonic signal based on a received pilot tone energy. An accurate operation of the receiver, including but not limited to correct decoding of monophonic/stereophonic reception, can be based on the receiver operating with the same rated maximum system deviation (RMSD) as the received signal itself. Aspects of the disclosure describe a system and method of detecting and matching a receiver's RMSD to that of a received signal by demodulating a carrier bearing a an input signal over a first bandwidth, extracting a pilot energy signal from the input signal, and demodulating the carrier bearing the input signal over a second bandwidth if the pilot energy signal is within a pilot energy range for a first predetermined amount of time.

Abstract: The present disclosure describes systems and techniques relating to calculation of array statistics. According to an aspect of the described systems and techniques, a device includes: a memory configured to store a data array and a counter array, wherein the data array includes multiple values, and each of the multiple values is encoded in a respective row of the data array, and wherein the counter array includes multiple counters, respective columns of the counter array correspond to respective ones of the counters, and rows of the counter array correspond with bit significance positions spanning the multiple counters; and processor electronics configured to add up a number bits found in respective columns of the data array using respective ones of the multiple counters.

Abstract: In one or more embodiments, system(s), method(s), integrated circuit(s), physical layer(s), apparatus(es), System-on-Chip (SoC), various other hardware, computer-readable and/or executable instructions, and/or technique(s) are described that enable a subroutine to release control of a processing entity when the subroutine is incomplete. By so doing, the processing entity may be used by code outside of the subroutine, such as code that needs attention, and/or more-fully utilize its own processing power by being less idle.

Abstract: An access point configured to be implemented in a wireless network, the access point including a beacon module and a transmit module. The access point is configured to communicate with one or more client stations in the wireless network. The beacon module is configured to generate (i) a first beacon and (ii) a second beacon, wherein the first beacon is shorter in duration than the second beacon. The transmit module is configured to periodically transmit, to the one or more client stations in the wireless network, each of the first beacon and the second beacon. Each time the first beacon and the second beacon are transmitted by the transmit module, the first beacon is transmitted prior to the second beacon.

Abstract: In some implementations, a method includes receiving information in a storage device controller from one or more storage devices in a solid state drive system over one or more channels; and for information received over each of the one or more channels, determining whether a condition for sending the information received over the channel to a host device is satisfied, and sending the information received over the channel to the host device when the condition for sending the information is satisfied.

Abstract: A method of performing timing recovery in a receiver device includes receiving an oversampled signal corresponding to at least a first portion of a radio frequency signal received by the receiver device from a transmitter device. The oversampled signal is sampled at an oversampling rate that is higher than a baud rate of the receiver device. The method also includes estimating a first timing error using samples of the oversampled signal. Estimating the first timing error includes generating a first timing error signal indicative of the estimated first timing error. The method also includes adjusting, using the first timing error signal, at least one sampling rate at which received signals are sampled in the receiver device.

Abstract: An apparatus attenuates pseudo-differential signals on a plurality of conductors. The apparatus may also attenuate one or both of differential signals and common mode signals on the conductors. The signals may be Power Line Communication (PLC) signals. The apparatus includes a choke including a plurality of mutually coupled windings. The windings of the choke include a first winding and a plurality of second windings, the first winding having a number of turns equal to the sum of the number of turns of the second windings. Each of the second windings may have a substantial leakage inductance. The apparatus may further include one or more capacitors electrically coupled between windings of the choke.