Patents Assigned to Massively Parallel Technologies, Inc.
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Patent number: 10216692Abstract: A multiprocessor system on a chip (MPSoC) implements parallel processing and include a plurality of cores with inter-core communication. This communication is implemented by an on-chip switch fabric in communication with each core, or by shared memory in communication with each core. In another embodiment, a parallel processing system is implemented as a Howard Cascade and uses shared memory for implementing inter-chip communication. The parallel processing system includes a plurality of chips, each formed as an MPSoC, and implements communication between the chips using shared memory.Type: GrantFiled: June 17, 2010Date of Patent: February 26, 2019Assignee: Massively Parallel Technologies, Inc.Inventor: Kevin D. Howard
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Patent number: 10148425Abstract: An encryption system and method has processors and a memory system, the memory system configured to hold at least one macroblock, an encryption key, and machine-readable instructions for encrypting the macroblock. The instructions include instructions for dividing the macroblock into subblocks by rows and encrypting the rows, for dividing the macroblock into subblocks by columns and encrypting the columns, and for performing a combining cipher of the cipher blocks to produce a final ciphertext of the macroblock. In alternative embodiments, the macroblock is divided in dimensions in addition to rows and columns. In embodiments, ciphertext is chained by using its ciphertext as part of a key for later macroblocks of a sequence, or propagated into later sequences of macroblocks.Type: GrantFiled: August 3, 2017Date of Patent: December 4, 2018Assignee: Massively Parallel Technologies, Inc.Inventor: Kevin D. Howard
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Patent number: 10009168Abstract: An encryption system and method has processors and a memory system, the memory system configured to hold at least one macroblock, an encryption key, and machine readable instructions for encrypting the macroblock. The instructions include instructions for dividing the macroblock into at subblocks by rows and encrypting the rows, for dividing the macroblock into subblocks by columns and encrypting the columns, and for performing a combining cipher of the first, second, third and fourth cipher blocks to produce a final ciphertext of the macroblock. In alternative embodiments, the macroblock is divided in a third, or fourth dimension in addition to rows and columns. In embodiments, ciphertext is chained by using it ciphertext as part of a key for later macroblocks of a sequence, or propagated into later sequences of macroblocks.Type: GrantFiled: November 26, 2013Date of Patent: June 26, 2018Assignee: Massively Parallel Technologies, Inc.Inventor: Kevin D. Howard
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Patent number: 9977655Abstract: System, methods, and software products automatically extract software design from a requirements document. A requirements hierarchical decomposition table is generated from the requirements document defining a plurality of decomposition levels. An initial hierarchical decomposition design having a plurality of decomposition levels based upon the requirements hierarchical decomposition table is generated. Input and/or output parameters for each decomposition level in the hierarchical decomposition design are identified, and a current hierarchical decomposition design is generated based upon the initial hierarchical decomposition graph and the input and/or output parameters.Type: GrantFiled: December 29, 2015Date of Patent: May 22, 2018Assignee: Massively Parallel Technologies, Inc.Inventor: Kevin D. Howard
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Patent number: 9747080Abstract: A system, method and software product shares a software design. A design sharer having machine readable instructions stored within memory of a development server and executable by a processor of the development server interacts with a first user to select a first portion of a first hierarchical software design. The design sharer saves the first portion within a public workspace. The design sharer interacts with a second user having access to the public workspace to select the first portion and inserts the first portion into a second hierarchical software design.Type: GrantFiled: March 7, 2016Date of Patent: August 29, 2017Assignee: Massively Parallel Technologies, Inc.Inventor: Kevin D. Howard
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Patent number: 9626329Abstract: Parallel Processing Communication Accelerator (PPCA) systems and methods for enhancing performance of a Parallel Processing Environment (PPE). In an embodiment, a Message Passing Interface (MPI) devolver enabled PPCA is in communication with the PPE and a host node. The host node executes at least a parallel processing application and an MPI process. The MPI devolver communicates with the MPI process and the PPE to improve the performance of the PPE by offloading MPI process functionality to the PPCA. Offloading MPI processing to the PPCA frees the host node for other processing tasks, for example, executing the parallel processing application, thereby improving the performance of the PPE.Type: GrantFiled: July 22, 2013Date of Patent: April 18, 2017Assignee: Massively Parallel Technologies, Inc.Inventor: Kevin D. Howard
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Patent number: 9424168Abstract: Disclosed herein is a system and method for automatically generating a test for a design process. The present system and method compares a keyword list associated with a design process and keyword lists associated with kernels and/or algorithms, temporarily associating matching kernels and/or algorithms with the design process, testing the kernels and/or algorithms with an input and designates the best output as the expected output.Type: GrantFiled: April 15, 2014Date of Patent: August 23, 2016Assignee: Massively Parallel Technologies, Inc.Inventor: Kevin D. Howard
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Publication number: 20160226658Abstract: An encryption system and method has processors and a memory system, the memory system configured to hold at least one macroblock, an encryption key, and machine readable instructions for encrypting the macroblock. The instructions include instructions for dividing the macroblock into at subblocks by rows and encrypting the rows, for dividing the macroblock into subblocks by columns and encrypting the columns, and for performing a combining cipher of the first, second, third and fourth cipher blocks to produce a final ciphertext of the macroblock. In alternative embodiments, the macroblock is divided in a third, or fourth dimension in addition to rows and columns. In embodiments, ciphertext is chained by using it ciphertext as part of a key for later macroblocks of a sequence, or propagated into later sequences of macroblocks.Type: ApplicationFiled: November 26, 2013Publication date: August 4, 2016Applicant: Massively Parallel Technologies, Inc.Inventor: Kevin D. Howard
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Patent number: 9395954Abstract: A system and method for performing functional decomposition of a software design to generate a computer-executable FSM and a graphical representation of the design in a decomposition diagram stored in a program database with source code, test code, and other program data. The method includes searching for pre-existing software modules that meet program design requirements. Modules needing work are displayed on Gantt or PERT charts as tasks, and may be annotated with start dates, and completion dates. Percent complete of the design is automatically generated and updated, and may be displayed on the charts. The decomposition is automatically used to introduce error detection states into the FSM for recognizing invalid states and saving checkpoints, and for recognizing and repairing both race conditions and deadlock conditions in the design.Type: GrantFiled: December 2, 2015Date of Patent: July 19, 2016Assignee: Massively Parallel Technologies, Inc.Inventor: Kevin D. Howard
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Patent number: 9335974Abstract: A system, method and software product determine and display a complexity designation of a software design based upon a hierarchical functional decomposition design model. Within a development server, a number of decomposition levels in the software design, a number of subgraphs in the software design, and a number of processes in the software design are determined. A complexity designation for the software design based upon the number of decomposition levels and the average number of processes in the subgraphs is then determined and displayed.Type: GrantFiled: April 15, 2014Date of Patent: May 10, 2016Assignee: Massively Parallel Technologies, Inc.Inventor: Kevin D. Howard
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Patent number: 9324126Abstract: A system and method for communication in a parallel computing system is applied to a system having multiple processing units, each processing unit including processor(s), memory, and a network interface, where the network interface is adapted to support virtual connections. The memory has at least a portion of a parallel processing application program and a parallel processing operating system. The system has a network fabric between processing units. The method involves identifying need for communication by the first processing unit with a group of processing units, creating virtual connections between the processing units, and transferring data between the first processing units.Type: GrantFiled: January 14, 2014Date of Patent: April 26, 2016Assignee: Massively Parallel Technologies, Inc.Inventor: Kevin D. Howard
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Patent number: 9292263Abstract: A system and method for quickly discerning a process's completeness via graphical representation of processes by graphical objects with associated embedded symbols is disclosed. The present system and method decreases design time and increases personnel deployment efficiency.Type: GrantFiled: April 15, 2014Date of Patent: March 22, 2016Assignee: Massively Parallel Technologies, Inc.Inventor: Kevin D. Howard
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Patent number: 9280320Abstract: A system, method and software product shares a software design. A design sharer having machine readable instructions stored within memory of a development server and executable by a processor of the development server interacts with a first user to select a first portion of a first hierarchical software design. The design sharer saves the first portion within a public workspace. The design sharer interacts with a second user having access to the public workspace to select the first portion and inserts the first portion into a second hierarchical software design.Type: GrantFiled: June 16, 2014Date of Patent: March 8, 2016Assignee: Massively Parallel Technologies, Inc.Inventor: Kevin D. Howard
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Patent number: 9229688Abstract: A system and method for performing functional decomposition of a software design to generate a computer-executable FSM and a graphical representation of the design in a decomposition diagram stored in a program database with source code, test code, and other program data. The method includes searching for pre-existing software modules that meet program design requirements. Modules needing work are displayed on Gantt or PERT charts as tasks, and may be annotated with start dates, and completion dates. Percent complete of the design is automatically generated and updated, and may be displayed on the charts. The decomposition is automatically used to introduce error detection states into the FSM for recognizing invalid states and saving checkpoints, and for recognizing and repairing both race conditions and deadlock conditions in the design.Type: GrantFiled: March 14, 2014Date of Patent: January 5, 2016Assignee: Massively Parallel Technologies, Inc.Inventor: Kevin D. Howard
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Patent number: 9170909Abstract: An automatic profiling system and method determines an algorithm profile including performance predictability and pricing of a parallel processing algorithm.Type: GrantFiled: June 4, 2013Date of Patent: October 27, 2015Assignee: Massively Parallel Technologies, Inc.Inventor: Kevin D. Howard
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Patent number: 9158502Abstract: A system and method for tagging objects in a software design space includes a visual representation generator that presents a visual representation of a software design to a user, and a tag manager that is operable to allow the user to create and manage tags of each object within the software design space. Certain tags are only visible to users having specific access rights to the tag.Type: GrantFiled: April 15, 2014Date of Patent: October 13, 2015Assignee: Massively Parallel Technologies, Inc.Inventor: Kevin D. Howard
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Patent number: 9146709Abstract: A system and method for detecting decomposition errors in a parallel processing software design having at least two decomposition levels, where each decomposition level has at least one process. The system and method further identifies improper control flow, looping structure and/or dataflow within the software design and restructures the software design to remove any improper elements.Type: GrantFiled: June 7, 2013Date of Patent: September 29, 2015Assignee: Massively Parallel Technologies, Inc.Inventor: Kevin D. Howard
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Patent number: 9098638Abstract: A system and method for generating a specific level of software testing of algorithms and applications. A test plan, including input parameter values, expected output parameter values, and dataset size, is entered. The test plan is then executed, and results of the test are scored in accordance with predetermined software testing level definitions, yielding one of a predetermined possible testing levels achieved by the tested software.Type: GrantFiled: June 7, 2013Date of Patent: August 4, 2015Assignee: Massively Parallel Technologies, Inc.Inventor: Kevin D. Howard
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Patent number: 8959494Abstract: A system and method for performing functional decomposition of a software design to generate a computer-executable finite state machine. Initially, the software design is received in a form wherein functions in the software design are repetitively decomposed into (1) data and control transformations. Included between the functions are control flow indicators which have transformation-selection conditions associated therewith. The data transformations and the control transformations are translated into states in the finite state machine. The transformation-selection conditions associated with the control transformations are translated into state transitions in the finite state machine.Type: GrantFiled: March 20, 2012Date of Patent: February 17, 2015Assignee: Massively Parallel Technologies Inc.Inventor: Kevin D. Howard
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Patent number: 8949796Abstract: A system and method for automatic code-design and file/database-design association. Existing source code is analyzed for process and control elements. The control elements are encapsulated as augmented state machines and the process elements are encapsulated as kernels. The new elements can then have meta-data attached (including, a name, I/O method, and test procedures), allowing software code sharing and automatic code/file/database upgrading, as well as allowing sub-subroutine level code blocks to be accessed directly.Type: GrantFiled: June 23, 2014Date of Patent: February 3, 2015Assignee: Massively Parallel Technologies, Inc.Inventor: Kevin D. Howard