Abstract: Methods and systems for parallel computation of an algorithm using a plurality of nodes configured as a Howard Cascade. A home node of a Howard Cascade receives a request from a host system to compute an algorithm identified in the request. The request is distributed to processing nodes of the Howard Cascade in a time sequence order in a manner to minimize the time to so expand the Howard Cascade. The participating nodes then perform the designated portion of the algorithm in parallel. Partial results from each node are agglomerated upstream to higher nodes of the structure and then returned to the host system. The nodes each include a library of stored algorithms accompanied by data template information defining partitioning of the data used in the algorithm among the number of participating nodes.
Type:
Grant
Filed:
August 25, 2008
Date of Patent:
June 1, 2010
Assignee:
Massively Parallel Technologies, Inc.
Inventors:
Kevin David Howard, Glen Curtis Rea, Nick Wade Robertson, Silva Chang
Abstract: Systems and methods form and control a supercomputer based upon a parallel processing architecture such as a Howard cascade. A graphical user interface allows a user to interact with one or more virtual power centers of the supercomputer facility. A plurality of processing nodes self-organize into one or more virtual power centers. The processing nodes utilize overlapped input and output for improved communication.
Type:
Application
Filed:
August 31, 2007
Publication date:
March 19, 2009
Applicant:
MASSIVELY PARALLEL TECHNOLOGIES, INC.
Inventors:
Kevin Howard, James Lupo, Thomas Geske, Nick Robertson
Abstract: Methods and systems for parallel computation of an algorithm using a plurality of nodes configured as a Howard Cascade. A home node of a Howard Cascade receives a request from a host system to compute an algorithm identified in the request. The request is distributed to processing nodes of the Howard Cascade in a time sequence order in a manner to minimize the time to so expand the Howard Cascade. The participating nodes then perform the designated portion of the algorithm in parallel. Partial results from each node are agglomerated upstream to higher nodes of the structure and then returned to the host system. The nodes each include a library of stored algorithms accompanied by data template information defining partitioning of the data used in the algorithm among the number of participating nodes.
Type:
Grant
Filed:
January 10, 2003
Date of Patent:
August 26, 2008
Assignee:
Massively Parallel Technologies, Inc.
Inventors:
Kevin David Howard, Glen Curtis Rea, Nick Wade Robertson, Silva Chang
Abstract: Systems and methods form and control a supercomputer based upon a parallel processing architecture such as a Howard cascade. A graphical user interface allows a user to interact with one or more virtual power centers of the supercomputer facility. A plurality of processing nodes self-organize into one or more virtual power centers. The processing nodes utilize overlapped input and output for improved communication.
Type:
Application
Filed:
August 31, 2007
Publication date:
April 3, 2008
Applicant:
MASSIVELY PARALLEL TECHNOLOGIES, INC.
Inventors:
Kevin Howard, James Lupo, Thomas Geske, Nick Robertson
Abstract: Methods and systems are provided for accelerating execution of programs of the type run by individuals or companies. The methods include the steps of communicating at least one program function to a library in data communication with the program and transmitting the function to a computing facility, typically in the form of computer clusters. The function is processed at the computing facility and results are relayed back to the user of the programs. Users of the invention pay for accelerated execution by one of several interfaces, such as through on-line transactions and/or through prearranged ISP connectivity. Accelerated processing is initiated, typically, by clicking on a computer icon; and results appear seamlessly—though accelerated—to the user. The clusters of the invention can mix and match computers of different processing speeds to maximize the MIPS per dollar in processing accelerated functions for users.
Type:
Grant
Filed:
June 26, 2000
Date of Patent:
February 15, 2005
Assignee:
Massively Parallel Technologies, Inc.
Inventors:
Kevin D. Howard, Gerard A. Verbeck, Scott A. Smith