Abstract: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

Abstract: A method of selecting numbers of sub-array groups for simultaneous operation to optimize bandwidth biases a number of sub-array groups and compares a circuit state value, preferably voltage, to a reference parameter to determine if the operation can successfully be preformed for that number of sub-array groups. The comparison may be repeated with ifferent numbers of sub-array groups biased to find the optimum number of sub-array groups for the operation.

Abstract: A three-dimensional, field-programmable, non-volatile memory includes multiple layers of first and second crossing conductors. Pillars are self-aligned at the intersection of adjacent first and second crossing conductors, and each pillar includes at least an anti-fuse layer. The pillars form memory cells with the adjacent conductors, and each memory cell includes first and second diode components separated by the anti-fuse layer. The diode components form a diode only after the anti-fuse layer is disrupted.

Abstract: A semiconductor device comprises two transistors where a gate electrode of one transistor and source or drain of another transistor are located in the same rail. A monolithic three dimensional array contains a plurality of such devices. The transistors in different levels of the array preferably have a different orientation.

Abstract: The preferred embodiments described herein provide a memory device and method for reading data stored in a portion of a memory device unreadable by a file system of a host device. In one preferred embodiment, a memory device is provided comprising a first portion that is readable by a file system of a host device and a second portion that is unreadable by the file system of the host device. The first portion stores program code operative to enable the host device to read the second portion. In operation, after the memory device is connected with the host device, the program code is provided to the host device, and the host device reads the data stored in the second portion of the memory device. Other preferred embodiments are provided, and each of the preferred embodiments described herein can be used alone or in combination with one another.

Abstract: A memory cell for a three-dimensional intergrated circuit memory is disclosed. The cell includes a very highly doped semiconductor regions with a doping level of 1020 atoms cm−3 or higher. An antifuse region is disposed between the heavily doped region and a more lightly doped region.

Abstract: An apparatus including a circuit of n circuit levels formed over a substrate from a first level to a nth level, wherein n is greater than one, and each of the n circuit levels has a material parameter change that is at least in part caused by a thermal processing operation that is applied to more than one of the n circuit levels simultaneously. An apparatus including a circuit of a plurality of circuit levels, each of the plurality of circuit levels having substantially similar material parameters.

Abstract: A semiconductor device contains a word line, a charge storage region located above the word line, an active layer located above the charge storage region, a patterned etch stop layer located above a first portion of the active layer, and bit lines located over a portion of the etch stop layer and over second portions of the active layer.

Abstract: A multiple-mode memory includes a three-dimensional array of word lines, bit lines and memory cells. The memory cells are arranged in multiple vertically stacked layers. In some layers the memory cells are implemented as field-programmable write-once memory cells, and in other layers the memory cells are implemented as field-programmable re-writable memory cells. In this way, both re-writability and permanent data storage are provided in an inexpensive, single-chip solution. Additional types and numbers of types of memory cells can be used.

Abstract: A three-dimensional memory array includes a plurality of rail-stacks on each of several levels forming alternating levels of X-lines and Y-lines for the array. Memory cells are formed at the intersection of each X-line and Y-line. The memory cells of each memory plane are all oriented in the same direction relative to the substrate, forming a serial chain diode stack. In certain embodiments, row and column circuits for the array are arranged to interchange function depending upon the directionality of memory cells in the selected memory plane. High-voltage drivers for the X-lines and Y-lines are each capable of passing a write current in either direction depending on the direction of the selected memory cell. A preferred bias arrangement reverse biases only unselected memory cells within the selected memory plane, totaling approximately N2 memory cells, rather than approximately 3N2 memory cells as with prior arrays.

Abstract: The present invention is directed to novel antifuse arrays and their methods of fabrication. According to an embodiment of the present invention an array comprises a plurality of first spaced apart rail-stacks having a top semiconductor material. A fill dielectric is located between the first plurality of spaced apart rail-stacks wherein the fill dielectric extends above the top surface of the semiconductor material. An antifuse material is formed on the top of the semiconductor material of the first plurality of spaced apart rail-stacks. A second plurality of spaced apart rail-stacks having a lower semiconductor material is formed on the antifuse material. In the second embodiment of the present invention the array comprises a first plurality of spaced apart rail-stacks having a top semiconductor material. A fill dielectric is located between the first plurality of spaced apart rail-stacks wherein the fill dielectric is recessed below the top surface of the semiconductor material.

Abstract: Support circuitry for a three-dimensional memory array is formed in a substrate at least partially under the three-dimensional memory array and defines open area in the substrate under the three-dimensional memory array. In one preferred embodiment, one or more memory arrays are formed at least partially in the open area under the three-dimensional memory array, while in another preferred embodiment, logic circuitry implementing one or more functions is formed at least partially in the open area under the three-dimensional memory array. In yet another preferred embodiment, both one or more memory arrays and logic circuitry are formed at least partially in the open area under the three-dimensional memory array. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.

Abstract: A three-dimensional memory array includes a plurality of rail-stacks on each of several levels forming alternating levels of X-lines and Y-lines for the array. Memory cells are formed at the intersection of each X-line and Y-line. The memory cells of each memory plane are all oriented in the same direction relative to the substrate, forming a serial chain diode stack. In certain embodiments, row and column circuits for the array are arranged to interchange function depending upon the directionality of memory cells in the selected memory plane. High-voltage drivers for the X-lines and Y-lines are each capable of passing a write current in either direction depending on the direction of the selected memory cell. A preferred bias arrangement reverse biases only unselected memory cells within the selected memory plane, totaling approximately N2 memory cells, rather than approximately 3N2 memory cells as with prior arrays.

Abstract: A thin dielectric layer grown on a silicide layer can be used in many semiconductor devices. Such a grown dielectric, which may be, for example, a silicon oxide, silicon nitride, or silicon oxynitride dielectric layer, can advantageously be used as a dielectric antifuse. Such an antifuse paired with a diode or diode portions can operate as a memory cell, which is unprogrammed before rupture and programmed after rupture. Memory cell types using a dielectric grown on a silicide include Schottky diode portions separated by an antifuse, a Schottky diode separated from an adjacent conductor by an antifuse, and a junction diode separated from an adjacent conductor by an antifuse.

Abstract: A nonvolatile multibank memory on a die with multiple read, write, and erase circuits, allowing more than one bank to be read, written, erased, or tested independently. Such a multibank memory arrangement is used advantageously in a monolithic three dimensional memory formed above a substrate, leaving unused substrate area available in which the additional circuitry and related cache memory can be formed.

Abstract: A semiconductor device comprises two transistors where a gate electrode of one transistor and source or drain of another transistor are located in the same rail. A monolithic three dimensional array contains a plurality of such devices. The transistors in different levels of the array preferably have a different orientation.

Abstract: The preferred embodiments described herein provide a memory device and methods for use therewith. In one preferred embodiment, a method is presented for using a file system to dynamically respond to variability in an indicated minimum number of memory cells of first and second write-once memory devices. In another preferred embodiment, a method for overwriting data in a memory device is described in which an error code is disregarded after a destructive pattern is written. In yet another preferred embodiment, a method is presented in which, after a block of memory has been allocated for a file to be stored in a memory device, available lines in that block are determined. Another preferred embodiment relates to reserving at least one memory cell in a memory device for file structures or file system structures. A memory device is also provided in which file system structures of at least two file systems are stored in the same memory partition.

Abstract: The preferred embodiments described herein provide a memory device with row and column decoder circuits arranged in a checkerboard pattern under a plurality of memory arrays. In one preferred embodiment, a memory device is provided with its row decoder circuits and column decoder circuits arranged in a checkerboard pattern under a plurality of memory arrays. Because each of the row decoder and column decoder circuits is associated with the memory array above its location and an adjacent array, a denser support circuit arrangement is provided as compared to prior approaches. Other preferred embodiments are provided, and each of the preferred embodiments described herein can be used alone or in combination with one another.

Abstract: The preferred embodiments described herein provide a memory device and method for temperature-based control over write and/or read operations. In one preferred embodiment, the temperature of a memory array is monitored, and a write operation to the memory array is prevented in response to the monitored temperature reaching a threshold temperature. In another preferred embodiment, the temperature of a memory array is monitored, and a read operation from the memory array is prevented in response to the monitored temperature reaching a threshold temperature. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.

Abstract: A multi-chip memory module may be formed including two or more stacked integrated circuits mounted to a substrate or lead frame structure. The memory module may include means to couple one or more of the stacked integrated circuits to edge conductors in a memory card package configuration. Such means may include the capability to utilize bonding pads on all four sides of an integrated circuit. A lead frame structure may be divided into first and second portions. The first portion may be adapted to receive the stacked integrated circuits and the second portion may include a plurality of conductors. The first portion may also be adapted to couple at least one of the integrated circuits to power and ground conductors on the second portion. In one embodiment, the first portion may include the lead frame paddle and a conductive ring. In another embodiment, the first portion may include first and second coplanar elements.