Abstract: A semiconductor light emitting device of the present invention includes: a substrate; a light emitting layer; a semiconductor layer of a hexagonal first III-group nitride crystal; and a cladding layer of a second III-group nitride crystal. A stripe groove is provided in the semiconductor layer along a <1, 1, −2, 0> direction.

Abstract: Through holes are provided in the inner electrodes of a second semiconductor chip, electrodes capable of being plated by electroless plating are formed on the inner walls of the through holes while being insulated from other electrodes, the second semiconductor chip is secured with an adhesive to a first semiconductor chip at portions other than the outer electrodes and the inner electrodes of the first semiconductor chip so that the inner electrodes of the first semiconductor chip are aligned with the inner electrodes of the second semiconductor chip, and the inner electrodes and the electrodes on the inner walls of the through holes are electrically connected to each other by continuously extending metals having the same composition. Therefore, a plurality of chips can be stacked without being damaged.

Abstract: An electronic device includes a wiring board, and at least one pair of signal lines that is provided on the wiring board in parallel and has an equal length. A chip is mounted on the wiring board and includes at least one differential driver which outputs complementary digital transmit signals to said at least one of lines. A pair of power system lines is provided to supply first and second power supply voltages to the above-mentioned at least one differential driver. The power system lines are parallel to each other and have an equal length.

Abstract: A semiconductor device includes a substrate, a multi-layer structure provided on the substrate, a first-conductive-type etch stop layer of a III nitride provided on the multi-layer structure, and a second-conductive-type first semiconductor layer of a III nitride provided on the etch stop layer. A molar fraction of Al is lower in a composition of the III nitride included in the first semiconductor layer than in a composition of the III nitride included in the etch stop layer.

Abstract: A lateral bipolar transistor includes: a substrate; a first insulative region formed on the substrate; a first semiconductor region of a first conductivity type selectively formed on the first insulative region; a second insulative region formed so as to substantially cover the first semiconductor region; and a second semiconductor region of a second conductivity type different from the first conductivity type, a second semiconductor region being selectively formed, wherein: the second insulative region has a first opening which reaches a surface of the first semiconductor region, and the first semiconductor region has a second opening which reaches the underlying first insulative region, the second opening being provided in a position corresponding to the first opening of the second insulative region; the second semiconductor region is formed so as to fill the first opening and the second opening, thereby functioning as a bass region; a lower portion of the second semiconductor region which at least fills th

Abstract: After an organic insulating film has been deposited over a semiconductor substrate, a silylated layer is formed selectively on the organic insulating film. Then, the organic insulating film is etched using the silylated layer as a mask, thereby forming an opening, which will be a via hole or interconnection groove, in the organic insulating film.

Abstract: A capacitor includes lower electrode, capacitive insulating film, upper electrode and passivation film that are formed in this order on a substrate. The capacitive insulating film is made of an insulating metal oxide, the metal oxide being a ferroelectric or a dielectric with a high relative dielectric constant. At least one contact hole is formed in the passivation film to connect the lower electrode to an interconnect for the lower electrode or the upper electrode to an interconnect for the upper electrode. The opening area of the contact hole is equal to or smaller than 5 &mgr;m2.

Abstract: A method for producing a semiconductor element comprises the steps of: forming a plurality of grooves on a first surface of a semiconductor multi-layer structure along a first direction: forming a plurality of multi-element bars by cleaving the semiconductor multi-layer structure along a second direction; placing at least one of the plurality of multi-element bars on a support stage; and cleaving the at least one of the plurality of multi-element bars along the plurality of grooves by moving a pressure member in a longitudinal direction of the at least one of the plurality of multi-element bars while a constant load is applied by the pressure member to a second surface of the at least one of the plurality of multi-element bars, the second surface being opposite a third surface corresponding to the first surface of the at least one of the plurality of multi-element bars.

Abstract: An optoelectronic apparatus includes an optoelectronic device, a mounting portion, a frame member surrounding a periphery of the mounting portion, and an optical component. The optical component is placed on an optical component placement portion. The frame member includes a pair of first side walls and a pair of second side walls. Each of the pair of second side walls has a recessed portion and a protruded portion. The optical component is disposed between the protruded portions, and is fixed with an adhesive filled in the recessed portions.

Abstract: An impurity introducing apparatus of the present invention includes: a system for introducing an impurity having charges into a target to be processed, the target being a semiconductor substrate or a film formed on the substrate; a system for supplying electrons into the target, the electrons canceling the charges of the impurity; and a system for controlling the maximum energy of the electrons supplied by the electron supply system at a predetermined value or less.

Abstract: Signal wirings 22, 23 are formed on a pair of substrates 20, 21, and the substrates are joined together through an insulating layer 24 so that the signal wirings 22, 23 are placed in parallel and facing to each other. The surfaces of the overlapping faces of the signal wirings 22, 23 are made smooth, and the roughness of the same surfaces is smaller than the skin depth &dgr;s due to the skin effect, preferably less than one third, for minimizing the increase in the electric resistance due to the skin effect.

Abstract: A terminal land frame includes a frame body and a plurality of lands. Each of these lands is formed out of the frame body to be connected to the frame body via a thinned portion and protrude therefrom. When the lands are pressed in a direction in which the lands protrude from the frame body, the thinned portions are fractured and the lands are easily separable from the frame body. A semiconductor chip is mounted on some of the lands of the terminal land frame, and the chip, wires and so on, are single-side-molded with a resin encapsulant. Thereafter, when the lands are pressed on the bottom, the lands are separated from the frame body. As a result, a structure, in which the lower part of each of these lands protrudes downward from the lower surface of the resin encapsulant, is obtained, and that protruding portion is used as an external electrode. In this manner, a downsized and thinned resin-molded semiconductor device is provided at a lower cost and with higher reliability.

Abstract: A gate insulator film and a gate electrode are formed on an Si substrate, and a CVD insulator film is deposited thereon to cover the gate electrode. Then, arsenic ions are implanted into the Si substrate from above the CVD insulator film to form LDD layers. After sidewall spacers have been formed over the side faces of the gate electrode with the CVD insulator film interposed therebetween, source/drain layers are formed. Since the LDD layers are formed by implanting dopant ions through the CVD insulator film, the passage of arsenic ions through the ends of the gate electrode can be suppressed. As a result, a semiconductor device suitable for miniaturization can be formed, while suppressing deterioration in insulating properties of the gate oxide film due to the passage of dopant ions through the ends of the gate electrode.

Abstract: Providing a light bulb having a long life by preventing filament coil breakage. A glass bulb (1) has a sealing portion (4) at one end thereof and contains a filament coil (5). The filament coil (5) is suspended between lead-in wires (7, 8) extended externally of the sealing portion (4), with its opposite ends connected to respective one ends of the wires. The lead-in wires (7, 8) are supported by a stem (6) disposed between the sealing portion (4) and the filament coil (5). A getter (9) is disposed between the sealing portion (4) and the stem (6).

Abstract: In a multi-layer interconnection structure, the wiring length is to be reduced, and the interconnection is to be straightened, at the same time as measures need to be taken against radiation noise. To this end, there is disclosed a semiconductor device in which plural semiconductor substrates, each carrying semiconductor elements, are bonded together. On each semiconductor substrate is deposited an insulating layer through which is formed a connection wiring passed through the insulating layer so as to be connected to the interconnection layer of the semiconductor element. On a junction surface of at least one of the semiconductor substrates is formed an electrically conductive layer of an electrically conductive material in which an opening is bored in association with the connection wiring. The semiconductor substrates are bonded together by the solid state bonding technique to interconnect the connection wirings formed on each semiconductor substrate.

Abstract: The invention provides a floating gate semiconductor storage device equipped with an erase gate electrode that includes first and second diffusion layers, an isolation insulating film, a gate insulating film, a floating gate electrode, a control gate electrode, a capacitor dielectric film, an erase gate electrode and a tunneling insulating film. In manufacturing the semiconductor storage device, after forming the first and second diffusion layers in a semiconductor substrate, an insulating film for isolation is deposited on the semiconductor substrate. The insulating film for isolation is simultaneously or individually patterned into an isolation insulating film and first and second lower contact holes respectively reaching the first and second diffusion layers. The semiconductor device includes first and second contact members filled in the first and second lower contact holes to be in contact with the first and second diffusion layers.

Abstract: The present invention provides an inexpensive low-pressure mercury vapor discharge lamp having enhanced productivity. The low-pressure mercury vapor discharge lamp comprises an arc tube, a holder for holding the arc tube, a lighting circuit held on the opposite side of the holder from the arc tube and adapted for lighting the arc tube, a case having a screw portion provided at one end thereof and adapted for accommodating the lighting circuit, and a base threaded and fixed to the screw portion. A recessed groove is provided in a helical screw thread of the screw portion. The two lead wires (top lead wire and side lead wire) which are power source wires are respectively connected at one end thereof to the lighting circuit. The side lead wire is disposed along the groove and is sandwiched and fixed between the base and the screw portion.

Abstract: A protective insulating film is deposited over first and second field-effect transistors formed on a semiconductor substrate. A capacitor composed of a capacitor lower electrode, a capacitor insulating film composed of an insulating metal oxide film, and a capacitor upper electrode is formed on the protective insulating film. A first contact plug formed in the protective insulating film provides a direct connection between the capacitor lower electrode and an impurity diffusion layer of the first field-effect transistor. A second contact plug formed in the protective insulating film provides a direct connection between the capacitor upper electrode and an impurity diffusion layer of the second field-effect transistor.

Abstract: In a multi-layer interconnection structure, the wiring length is to be reduced, and the interconnection is to be straightened, at the same time as measures need to be taken against radiation noise. To this end, there is disclosed a semiconductor device in which plural semiconductor substrates, each carrying semiconductor elements, are bonded together. On each semiconductor substrate is deposited an insulating layer through which is formed a connection wiring passed through the insulating layer so as to be connected to the interconnection layer of the semiconductor element. On a junction surface of at least one of the semiconductor substrates is formed an electrically conductive layer of an electrically conductive material in which an opening is bored in association with the connection wiring. The semiconductor substrates are bonded together by the solid state bonding technique to interconnect the connection wirings formed on each semiconductor substrate.

Abstract: First, an isolation region is formed on a surface portion of a semiconductor substrate of silicon, thereby defining first and second regions, which are isolated from each other by the isolation region, on the semiconductor substrate. Next, a tantalum oxide film is formed in the first region on the semiconductor substrate. Then, a silicon dioxide film is formed in the second region on the semiconductor substrate by heat-treating the semiconductor substrate within an ambient containing oxygen as a main component. Subsequently, first and second gate electrodes are formed on the tantalum oxide and silicon dioxide films, respectively. Thereafter, first and second gate insulating films are formed by etching the tantalum oxide and silicon dioxide films using the first and second gate electrodes as respective masks.